[llvm] Add an LTO run to the quant_4x4 phase ordering test (NFC) (PR #210088)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 09:02:21 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Momchil Velikov (momchil-velikov)
<details>
<summary>Changes</summary>
---
Patch is 36.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210088.diff
1 Files Affected:
- (modified) llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll (+510)
``````````diff
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll
index 37b022ea78595..9bce5108f98ab 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -O3 < %s | FileCheck %s
+; RUN: opt -S --passes="lto-pre-link<O3>,lto<O3>" < %s | FileCheck %s -check-prefix=CHECK-LTO
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
@@ -516,6 +517,515 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) {
; CHECK-NEXT: [[OR_1550]] = or i16 [[OR_1449]], [[STOREMERGE_15]]
; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
;
+; CHECK-LTO-LABEL: define range(i32 0, 2) i32 @quant_4x4
+; CHECK-LTO-SAME: (ptr nofree noundef captures(none) [[DCT:%.*]], ptr nofree noundef readonly captures(none) [[MF:%.*]], ptr nofree noundef readonly captures(none) [[BIAS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {{.*}}{
+; CHECK-LTO-NEXT: entry:
+; CHECK-LTO-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DCT]], i64 32
+; CHECK-LTO-NEXT: [[SCEVGEP23:%.*]] = getelementptr i8, ptr [[BIAS]], i64 32
+; CHECK-LTO-NEXT: [[SCEVGEP24:%.*]] = getelementptr i8, ptr [[MF]], i64 32
+; CHECK-LTO-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DCT]], [[SCEVGEP23]]
+; CHECK-LTO-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[BIAS]], [[SCEVGEP]]
+; CHECK-LTO-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-LTO-NEXT: [[BOUND025:%.*]] = icmp ult ptr [[DCT]], [[SCEVGEP24]]
+; CHECK-LTO-NEXT: [[BOUND126:%.*]] = icmp ult ptr [[MF]], [[SCEVGEP]]
+; CHECK-LTO-NEXT: [[FOUND_CONFLICT27:%.*]] = and i1 [[BOUND025]], [[BOUND126]]
+; CHECK-LTO-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT27]]
+; CHECK-LTO-NEXT: br i1 [[CONFLICT_RDX]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY:%.*]]
+; CHECK-LTO: vector.body:
+; CHECK-LTO-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 16
+; CHECK-LTO-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[DCT]], align 2, !alias.scope [[META1:![0-9]+]], !noalias [[META4:![0-9]+]]
+; CHECK-LTO-NEXT: [[WIDE_LOAD28:%.*]] = load <8 x i16>, ptr [[TMP0]], align 2, !alias.scope [[META1]], !noalias [[META4]]
+; CHECK-LTO-NEXT: [[TMP1:%.*]] = sext <8 x i16> [[WIDE_LOAD]] to <8 x i32>
+; CHECK-LTO-NEXT: [[TMP2:%.*]] = sext <8 x i16> [[WIDE_LOAD28]] to <8 x i32>
+; CHECK-LTO-NEXT: [[TMP3:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD]], zeroinitializer
+; CHECK-LTO-NEXT: [[TMP4:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD28]], zeroinitializer
+; CHECK-LTO-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 16
+; CHECK-LTO-NEXT: [[WIDE_LOAD29:%.*]] = load <8 x i16>, ptr [[BIAS]], align 2, !alias.scope [[META7:![0-9]+]]
+; CHECK-LTO-NEXT: [[WIDE_LOAD30:%.*]] = load <8 x i16>, ptr [[TMP5]], align 2, !alias.scope [[META7]]
+; CHECK-LTO-NEXT: [[TMP6:%.*]] = zext <8 x i16> [[WIDE_LOAD29]] to <8 x i32>
+; CHECK-LTO-NEXT: [[TMP7:%.*]] = zext <8 x i16> [[WIDE_LOAD30]] to <8 x i32>
+; CHECK-LTO-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 16
+; CHECK-LTO-NEXT: [[WIDE_LOAD31:%.*]] = load <8 x i16>, ptr [[MF]], align 2, !alias.scope [[META8:![0-9]+]]
+; CHECK-LTO-NEXT: [[WIDE_LOAD32:%.*]] = load <8 x i16>, ptr [[TMP8]], align 2, !alias.scope [[META8]]
+; CHECK-LTO-NEXT: [[TMP9:%.*]] = zext <8 x i16> [[WIDE_LOAD31]] to <8 x i32>
+; CHECK-LTO-NEXT: [[TMP10:%.*]] = zext <8 x i16> [[WIDE_LOAD32]] to <8 x i32>
+; CHECK-LTO-NEXT: [[TMP11:%.*]] = sub nsw <8 x i32> [[TMP6]], [[TMP1]]
+; CHECK-LTO-NEXT: [[TMP12:%.*]] = sub nsw <8 x i32> [[TMP7]], [[TMP2]]
+; CHECK-LTO-NEXT: [[TMP13:%.*]] = mul <8 x i32> [[TMP11]], [[TMP9]]
+; CHECK-LTO-NEXT: [[TMP14:%.*]] = mul <8 x i32> [[TMP12]], [[TMP10]]
+; CHECK-LTO-NEXT: [[TMP15:%.*]] = lshr <8 x i32> [[TMP13]], splat (i32 16)
+; CHECK-LTO-NEXT: [[TMP16:%.*]] = lshr <8 x i32> [[TMP14]], splat (i32 16)
+; CHECK-LTO-NEXT: [[TMP17:%.*]] = trunc nuw <8 x i32> [[TMP15]] to <8 x i16>
+; CHECK-LTO-NEXT: [[TMP18:%.*]] = trunc nuw <8 x i32> [[TMP16]] to <8 x i16>
+; CHECK-LTO-NEXT: [[TMP19:%.*]] = sub <8 x i16> zeroinitializer, [[TMP17]]
+; CHECK-LTO-NEXT: [[TMP20:%.*]] = sub <8 x i16> zeroinitializer, [[TMP18]]
+; CHECK-LTO-NEXT: [[TMP21:%.*]] = add nuw nsw <8 x i32> [[TMP6]], [[TMP1]]
+; CHECK-LTO-NEXT: [[TMP22:%.*]] = add nuw nsw <8 x i32> [[TMP7]], [[TMP2]]
+; CHECK-LTO-NEXT: [[TMP23:%.*]] = mul <8 x i32> [[TMP21]], [[TMP9]]
+; CHECK-LTO-NEXT: [[TMP24:%.*]] = mul <8 x i32> [[TMP22]], [[TMP10]]
+; CHECK-LTO-NEXT: [[TMP25:%.*]] = lshr <8 x i32> [[TMP23]], splat (i32 16)
+; CHECK-LTO-NEXT: [[TMP26:%.*]] = lshr <8 x i32> [[TMP24]], splat (i32 16)
+; CHECK-LTO-NEXT: [[TMP27:%.*]] = trunc nuw <8 x i32> [[TMP25]] to <8 x i16>
+; CHECK-LTO-NEXT: [[TMP28:%.*]] = trunc nuw <8 x i32> [[TMP26]] to <8 x i16>
+; CHECK-LTO-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP27]], <8 x i16> [[TMP19]]
+; CHECK-LTO-NEXT: [[PREDPHI33:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP28]], <8 x i16> [[TMP20]]
+; CHECK-LTO-NEXT: store <8 x i16> [[PREDPHI]], ptr [[DCT]], align 2, !alias.scope [[META1]], !noalias [[META4]]
+; CHECK-LTO-NEXT: store <8 x i16> [[PREDPHI33]], ptr [[TMP0]], align 2, !alias.scope [[META1]], !noalias [[META4]]
+; CHECK-LTO-NEXT: [[BIN_RDX34:%.*]] = or <8 x i16> [[PREDPHI33]], [[PREDPHI]]
+; CHECK-LTO-NEXT: [[TMP29:%.*]] = tail call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[BIN_RDX34]])
+; CHECK-LTO-NEXT: br label [[FOR_COND_CLEANUP:%.*]]
+; CHECK-LTO: for.cond.cleanup:
+; CHECK-LTO-NEXT: [[OR_LCSSA_IN:%.*]] = phi i16 [ [[TMP29]], [[VECTOR_BODY]] ], [ [[OR_1550:%.*]], [[IF_END_15:%.*]] ]
+; CHECK-LTO-NEXT: [[TOBOOL:%.*]] = icmp ne i16 [[OR_LCSSA_IN]], 0
+; CHECK-LTO-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[TOBOOL]] to i32
+; CHECK-LTO-NEXT: ret i32 [[LNOT_EXT]]
+; CHECK-LTO: for.body:
+; CHECK-LTO-NEXT: [[TMP30:%.*]] = load i16, ptr [[DCT]], align 2
+; CHECK-LTO-NEXT: [[CONV:%.*]] = sext i16 [[TMP30]] to i32
+; CHECK-LTO-NEXT: [[CMP1:%.*]] = icmp sgt i16 [[TMP30]], 0
+; CHECK-LTO-NEXT: [[TMP31:%.*]] = load i16, ptr [[BIAS]], align 2
+; CHECK-LTO-NEXT: [[CONV5:%.*]] = zext i16 [[TMP31]] to i32
+; CHECK-LTO-NEXT: [[TMP32:%.*]] = load i16, ptr [[MF]], align 2
+; CHECK-LTO-NEXT: [[CONV11:%.*]] = zext i16 [[TMP32]] to i32
+; CHECK-LTO-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK-LTO: if.then:
+; CHECK-LTO-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV5]], [[CONV]]
+; CHECK-LTO-NEXT: [[MUL:%.*]] = mul i32 [[ADD]], [[CONV11]]
+; CHECK-LTO-NEXT: [[SHR:%.*]] = lshr i32 [[MUL]], 16
+; CHECK-LTO-NEXT: [[CONV12:%.*]] = trunc nuw i32 [[SHR]] to i16
+; CHECK-LTO-NEXT: br label [[IF_END:%.*]]
+; CHECK-LTO: if.else:
+; CHECK-LTO-NEXT: [[ADD21:%.*]] = sub nsw i32 [[CONV5]], [[CONV]]
+; CHECK-LTO-NEXT: [[MUL25:%.*]] = mul i32 [[ADD21]], [[CONV11]]
+; CHECK-LTO-NEXT: [[SHR26:%.*]] = lshr i32 [[MUL25]], 16
+; CHECK-LTO-NEXT: [[TMP33:%.*]] = trunc nuw i32 [[SHR26]] to i16
+; CHECK-LTO-NEXT: [[CONV28:%.*]] = sub i16 0, [[TMP33]]
+; CHECK-LTO-NEXT: br label [[IF_END]]
+; CHECK-LTO: if.end:
+; CHECK-LTO-NEXT: [[STOREMERGE:%.*]] = phi i16 [ [[CONV28]], [[IF_ELSE]] ], [ [[CONV12]], [[IF_THEN]] ]
+; CHECK-LTO-NEXT: store i16 [[STOREMERGE]], ptr [[DCT]], align 2
+; CHECK-LTO-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 2
+; CHECK-LTO-NEXT: [[TMP34:%.*]] = load i16, ptr [[ARRAYIDX_1]], align 2
+; CHECK-LTO-NEXT: [[CONV_1:%.*]] = sext i16 [[TMP34]] to i32
+; CHECK-LTO-NEXT: [[CMP1_1:%.*]] = icmp sgt i16 [[TMP34]], 0
+; CHECK-LTO-NEXT: [[ARRAYIDX4_1:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 2
+; CHECK-LTO-NEXT: [[TMP35:%.*]] = load i16, ptr [[ARRAYIDX4_1]], align 2
+; CHECK-LTO-NEXT: [[CONV5_1:%.*]] = zext i16 [[TMP35]] to i32
+; CHECK-LTO-NEXT: [[ARRAYIDX10_1:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 2
+; CHECK-LTO-NEXT: [[TMP36:%.*]] = load i16, ptr [[ARRAYIDX10_1]], align 2
+; CHECK-LTO-NEXT: [[CONV11_1:%.*]] = zext i16 [[TMP36]] to i32
+; CHECK-LTO-NEXT: br i1 [[CMP1_1]], label [[IF_THEN_1:%.*]], label [[IF_ELSE_1:%.*]]
+; CHECK-LTO: if.else.1:
+; CHECK-LTO-NEXT: [[ADD21_1:%.*]] = sub nsw i32 [[CONV5_1]], [[CONV_1]]
+; CHECK-LTO-NEXT: [[MUL25_1:%.*]] = mul i32 [[ADD21_1]], [[CONV11_1]]
+; CHECK-LTO-NEXT: [[SHR26_1:%.*]] = lshr i32 [[MUL25_1]], 16
+; CHECK-LTO-NEXT: [[TMP37:%.*]] = trunc nuw i32 [[SHR26_1]] to i16
+; CHECK-LTO-NEXT: [[CONV28_1:%.*]] = sub i16 0, [[TMP37]]
+; CHECK-LTO-NEXT: br label [[IF_END_1:%.*]]
+; CHECK-LTO: if.then.1:
+; CHECK-LTO-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[CONV5_1]], [[CONV_1]]
+; CHECK-LTO-NEXT: [[MUL_1:%.*]] = mul i32 [[ADD_1]], [[CONV11_1]]
+; CHECK-LTO-NEXT: [[SHR_1:%.*]] = lshr i32 [[MUL_1]], 16
+; CHECK-LTO-NEXT: [[CONV12_1:%.*]] = trunc nuw i32 [[SHR_1]] to i16
+; CHECK-LTO-NEXT: br label [[IF_END_1]]
+; CHECK-LTO: if.end.1:
+; CHECK-LTO-NEXT: [[STOREMERGE_1:%.*]] = phi i16 [ [[CONV28_1]], [[IF_ELSE_1]] ], [ [[CONV12_1]], [[IF_THEN_1]] ]
+; CHECK-LTO-NEXT: store i16 [[STOREMERGE_1]], ptr [[ARRAYIDX_1]], align 2
+; CHECK-LTO-NEXT: [[OR_136:%.*]] = or i16 [[STOREMERGE]], [[STOREMERGE_1]]
+; CHECK-LTO-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 4
+; CHECK-LTO-NEXT: [[TMP38:%.*]] = load i16, ptr [[ARRAYIDX_2]], align 2
+; CHECK-LTO-NEXT: [[CONV_2:%.*]] = sext i16 [[TMP38]] to i32
+; CHECK-LTO-NEXT: [[CMP1_2:%.*]] = icmp sgt i16 [[TMP38]], 0
+; CHECK-LTO-NEXT: [[ARRAYIDX4_2:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 4
+; CHECK-LTO-NEXT: [[TMP39:%.*]] = load i16, ptr [[ARRAYIDX4_2]], align 2
+; CHECK-LTO-NEXT: [[CONV5_2:%.*]] = zext i16 [[TMP39]] to i32
+; CHECK-LTO-NEXT: [[ARRAYIDX10_2:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 4
+; CHECK-LTO-NEXT: [[TMP40:%.*]] = load i16, ptr [[ARRAYIDX10_2]], align 2
+; CHECK-LTO-NEXT: [[CONV11_2:%.*]] = zext i16 [[TMP40]] to i32
+; CHECK-LTO-NEXT: br i1 [[CMP1_2]], label [[IF_THEN_2:%.*]], label [[IF_ELSE_2:%.*]]
+; CHECK-LTO: if.else.2:
+; CHECK-LTO-NEXT: [[ADD21_2:%.*]] = sub nsw i32 [[CONV5_2]], [[CONV_2]]
+; CHECK-LTO-NEXT: [[MUL25_2:%.*]] = mul i32 [[ADD21_2]], [[CONV11_2]]
+; CHECK-LTO-NEXT: [[SHR26_2:%.*]] = lshr i32 [[MUL25_2]], 16
+; CHECK-LTO-NEXT: [[TMP41:%.*]] = trunc nuw i32 [[SHR26_2]] to i16
+; CHECK-LTO-NEXT: [[CONV28_2:%.*]] = sub i16 0, [[TMP41]]
+; CHECK-LTO-NEXT: br label [[IF_END_2:%.*]]
+; CHECK-LTO: if.then.2:
+; CHECK-LTO-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[CONV5_2]], [[CONV_2]]
+; CHECK-LTO-NEXT: [[MUL_2:%.*]] = mul i32 [[ADD_2]], [[CONV11_2]]
+; CHECK-LTO-NEXT: [[SHR_2:%.*]] = lshr i32 [[MUL_2]], 16
+; CHECK-LTO-NEXT: [[CONV12_2:%.*]] = trunc nuw i32 [[SHR_2]] to i16
+; CHECK-LTO-NEXT: br label [[IF_END_2]]
+; CHECK-LTO: if.end.2:
+; CHECK-LTO-NEXT: [[STOREMERGE_2:%.*]] = phi i16 [ [[CONV28_2]], [[IF_ELSE_2]] ], [ [[CONV12_2]], [[IF_THEN_2]] ]
+; CHECK-LTO-NEXT: store i16 [[STOREMERGE_2]], ptr [[ARRAYIDX_2]], align 2
+; CHECK-LTO-NEXT: [[OR_237:%.*]] = or i16 [[OR_136]], [[STOREMERGE_2]]
+; CHECK-LTO-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 6
+; CHECK-LTO-NEXT: [[TMP42:%.*]] = load i16, ptr [[ARRAYIDX_3]], align 2
+; CHECK-LTO-NEXT: [[CONV_3:%.*]] = sext i16 [[TMP42]] to i32
+; CHECK-LTO-NEXT: [[CMP1_3:%.*]] = icmp sgt i16 [[TMP42]], 0
+; CHECK-LTO-NEXT: [[ARRAYIDX4_3:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 6
+; CHECK-LTO-NEXT: [[TMP43:%.*]] = load i16, ptr [[ARRAYIDX4_3]], align 2
+; CHECK-LTO-NEXT: [[CONV5_3:%.*]] = zext i16 [[TMP43]] to i32
+; CHECK-LTO-NEXT: [[ARRAYIDX10_3:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 6
+; CHECK-LTO-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX10_3]], align 2
+; CHECK-LTO-NEXT: [[CONV11_3:%.*]] = zext i16 [[TMP44]] to i32
+; CHECK-LTO-NEXT: br i1 [[CMP1_3]], label [[IF_THEN_3:%.*]], label [[IF_ELSE_3:%.*]]
+; CHECK-LTO: if.else.3:
+; CHECK-LTO-NEXT: [[ADD21_3:%.*]] = sub nsw i32 [[CONV5_3]], [[CONV_3]]
+; CHECK-LTO-NEXT: [[MUL25_3:%.*]] = mul i32 [[ADD21_3]], [[CONV11_3]]
+; CHECK-LTO-NEXT: [[SHR26_3:%.*]] = lshr i32 [[MUL25_3]], 16
+; CHECK-LTO-NEXT: [[TMP45:%.*]] = trunc nuw i32 [[SHR26_3]] to i16
+; CHECK-LTO-NEXT: [[CONV28_3:%.*]] = sub i16 0, [[TMP45]]
+; CHECK-LTO-NEXT: br label [[IF_END_3:%.*]]
+; CHECK-LTO: if.then.3:
+; CHECK-LTO-NEXT: [[ADD_3:%.*]] = add nuw nsw i32 [[CONV5_3]], [[CONV_3]]
+; CHECK-LTO-NEXT: [[MUL_3:%.*]] = mul i32 [[ADD_3]], [[CONV11_3]]
+; CHECK-LTO-NEXT: [[SHR_3:%.*]] = lshr i32 [[MUL_3]], 16
+; CHECK-LTO-NEXT: [[CONV12_3:%.*]] = trunc nuw i32 [[SHR_3]] to i16
+; CHECK-LTO-NEXT: br label [[IF_END_3]]
+; CHECK-LTO: if.end.3:
+; CHECK-LTO-NEXT: [[STOREMERGE_3:%.*]] = phi i16 [ [[CONV28_3]], [[IF_ELSE_3]] ], [ [[CONV12_3]], [[IF_THEN_3]] ]
+; CHECK-LTO-NEXT: store i16 [[STOREMERGE_3]], ptr [[ARRAYIDX_3]], align 2
+; CHECK-LTO-NEXT: [[OR_338:%.*]] = or i16 [[OR_237]], [[STOREMERGE_3]]
+; CHECK-LTO-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 8
+; CHECK-LTO-NEXT: [[TMP46:%.*]] = load i16, ptr [[ARRAYIDX_4]], align 2
+; CHECK-LTO-NEXT: [[CONV_4:%.*]] = sext i16 [[TMP46]] to i32
+; CHECK-LTO-NEXT: [[CMP1_4:%.*]] = icmp sgt i16 [[TMP46]], 0
+; CHECK-LTO-NEXT: [[ARRAYIDX4_4:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 8
+; CHECK-LTO-NEXT: [[TMP47:%.*]] = load i16, ptr [[ARRAYIDX4_4]], align 2
+; CHECK-LTO-NEXT: [[CONV5_4:%.*]] = zext i16 [[TMP47]] to i32
+; CHECK-LTO-NEXT: [[ARRAYIDX10_4:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 8
+; CHECK-LTO-NEXT: [[TMP48:%.*]] = load i16, ptr [[ARRAYIDX10_4]], align 2
+; CHECK-LTO-NEXT: [[CONV11_4:%.*]] = zext i16 [[TMP48]] to i32
+; CHECK-LTO-NEXT: br i1 [[CMP1_4]], label [[IF_THEN_4:%.*]], label [[IF_ELSE_4:%.*]]
+; CHECK-LTO: if.else.4:
+; CHECK-LTO-NEXT: [[ADD21_4:%.*]] = sub nsw i32 [[CONV5_4]], [[CONV_4]]
+; CHECK-LTO-NEXT: [[MUL25_4:%.*]] = mul i32 [[ADD21_4]], [[CONV11_4]]
+; CHECK-LTO-NEXT: [[SHR26_4:%.*]] = lshr i32 [[MUL25_4]], 16
+; CHECK-LTO-NEXT: [[TMP49:%.*]] = trunc nuw i32 [[SHR26_4]] to i16
+; CHECK-LTO-NEXT: [[CONV28_4:%.*]] = sub i16 0, [[TMP49]]
+; CHECK-LTO-NEXT: br label [[IF_END_4:%.*]]
+; CHECK-LTO: if.then.4:
+; CHECK-LTO-NEXT: [[ADD_4:%.*]] = add nuw nsw i32 [[CONV5_4]], [[CONV_4]]
+; CHECK-LTO-NEXT: [[MUL_4:%.*]] = mul i32 [[ADD_4]], [[CONV11_4]]
+; CHECK-LTO-NEXT: [[SHR_4:%.*]] = lshr i32 [[MUL_4]], 16
+; CHECK-LTO-NEXT: [[CONV12_4:%.*]] = trunc nuw i32 [[SHR_4]] to i16
+; CHECK-LTO-NEXT: br label [[IF_END_4]]
+; CHECK-LTO: if.end.4:
+; CHECK-LTO-NEXT: [[STOREMERGE_4:%.*]] = phi i16 [ [[CONV28_4]], [[IF_ELSE_4]] ], [ [[CONV12_4]], [[IF_THEN_4]] ]
+; CHECK-LTO-NEXT: store i16 [[STOREMERGE_4]], ptr [[ARRAYIDX_4]], align 2
+; CHECK-LTO-NEXT: [[OR_439:%.*]] = or i16 [[OR_338]], [[STOREMERGE_4]]
+; CHECK-LTO-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 10
+; CHECK-LTO-NEXT: [[TMP50:%.*]] = load i16, ptr [[ARRAYIDX_5]], align 2
+; CHECK-LTO-NEXT: [[CONV_5:%.*]] = sext i16 [[TMP50]] to i32
+; CHECK-LTO-NEXT: [[CMP1_5:%.*]] = icmp sgt i16 [[TMP50]], 0
+; CHECK-LTO-NEXT: [[ARRAYIDX4_5:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 10
+; CHECK-LTO-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4_5]], align 2
+; CHECK-LTO-NEXT: [[CONV5_5:%.*]] = zext i16 [[TMP51]] to i32
+; CHECK-LTO-NEXT: [[ARRAYIDX10_5:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 10
+; CHECK-LTO-NEXT: [[TMP52:%.*]] = load i16, ptr [[ARRAYIDX10_5]], align 2
+; CHECK-LTO-NEXT: [[CONV11_5:%.*]] = zext i16 [[TMP52]] to i32
+; CHECK-LTO-NEXT: br i1 [[CMP1_5]], label [[IF_THEN_5:%.*]], label [[IF_ELSE_5:%.*]]
+; CHECK-LTO: if.else.5:
+; CHECK-LTO-NEXT: [[ADD21_5:%.*]] = sub nsw i32 [[CONV5_5]], [[CONV_5]]
+; CHECK-LTO-NEXT: [[MUL25_5:%.*]] = mul i32 [[ADD21_5]], [[CONV11_5]]
+; CHECK-LTO-NEXT: [[SHR26_5:%.*]] = lshr i32 [[MUL25_5]], 16
+; CHECK-LTO-NEXT: [[TMP53:%.*]] = trunc nuw i32 [[SHR26_5]] to i16
+; CHECK-LTO-NEXT: [[CONV28_5:%.*]] = sub i16 0, [[TMP53]]
+; CHECK-LTO-NEXT: br label [[IF_END_5:%.*]]
+; CHECK-LTO: if.then.5:
+; CHECK-LTO-NEXT: [[ADD_5:%.*]] = add nuw nsw i32 [[CONV5_5]], [[CONV_5]]
+; CHECK-LTO-NEXT: [[MUL_5:%.*]] = mul i32 [[ADD_5]], [[CONV11_5]]
+; CHECK-LTO-NEXT: [[SHR_5:%.*]] = lshr i32 [[MUL_5]], 16
+; CHECK-LTO-NEXT: [[CONV12_5:%.*]] = trunc nuw i32 [[SHR_5]] to i16
+; CHECK-LTO-NEXT: br label [[IF_END_5]]
+; CHECK-LTO: if.end.5:
+; CHECK-LTO-NEXT: [[STOREMERGE_5:%.*]] = phi i16 [ [[CONV28_5]], [[IF_ELSE_5]] ], [ [[CONV12_5]], [[IF_THEN_5]] ]
+; CHECK-LTO-NEXT: store i16 [[STOREMERGE_5]], ptr [[ARRAYIDX_5]], align 2
+; CHECK-LTO-NEXT: [[OR_540:%.*]] = or i16 [[OR_439]], [[STOREMERGE_5]]
+; CHECK-LTO-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 12
+; CHECK-LTO-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX_6]], align 2
+; CHECK-LTO-NEXT: [[CONV_6:%.*]] = sext i16 [[TMP54]] to i32
+; CHECK-LTO-NEXT: [[CMP1_6:%.*]] = icmp sgt i16 [[TMP54]], 0
+; CHECK-LTO-NEXT: [[ARRAYIDX4_6:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 12
+; CHECK-LTO-NEXT: [[TMP55:%.*]] = load i16, ptr [[ARRAYIDX4_6]], align 2
+; CHECK-LTO-NEXT: [[CONV5_6:%.*]] = zext i16 [[TMP55]] to i32
+; CHECK-LTO-NEXT: [[ARRAYIDX10_6:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 12
+; CHECK-LTO-NEXT: [[TMP56:%.*]] = load i16, ptr [[ARRAYIDX10_6]], align 2
+; CHECK-LTO-NEXT: [[CONV11_6:%.*]] = zext i16 [[TMP56]] to i32
+; CHECK-LTO-NEXT: br i1 [[CMP1_6]], label [[IF_THEN_6:%.*]], label [[IF_ELSE_6:%.*]]
+; CHECK-LTO: if.else.6:
+; CHECK-LTO-NEXT: [[ADD21_6:%.*]] = sub nsw i32 [[CONV5_6]], [[CONV_6]]
+; CHECK-LTO-NEXT: [[MUL25_6:%.*]] = mul i32 [[ADD21_6]], [[CONV11_6]]
+; CHECK-LTO-NEXT: [[SHR26_6:%.*]] = lshr i32 [[MUL25_6]], 16
+; CHECK-LTO-NEXT: [[TMP57:%.*]] = trunc nuw i32 [[SHR26_6]] to i16
+; CHECK-LTO-NEXT: [[CONV28_6:%.*]] = sub i16 0, [[TMP57]]
+; CHECK-LTO-NEXT: br label [[IF_END_6:%.*]]
+; CHECK-LTO: if.then.6:
+; CHECK-LTO-NEXT: [[ADD_6:%.*]] = add nuw nsw i32 [[CONV5_6]], [[CONV_6]]
+; CHECK-LTO-NEXT: [[MUL_6:%.*]] = mul i32 [[ADD_6]], [[CONV11_6]]
+; CHECK-LTO-NEXT: [[SHR_6:%.*]] = lshr i32 [[MUL_6]], 16
+; CHECK-LTO-NEXT: [[CONV12_6:%.*]] = trunc nuw i32 [[SHR_6]] to i16
+; CHECK-LTO-NEXT: br label [[IF_END_6]]
+; CHECK-LTO: if.end.6:
+; CHECK-LTO-NEXT: [[STOREMERGE_6:%.*]] = phi i16 [ [[CONV28_6]], [[IF_ELSE_6]] ], [ [[CONV12_6]], [[IF_THEN_6]] ]
+; CHECK-LTO-NEXT: store i16 [[STOREMERGE_6]], ptr [[ARRAYIDX_6]], align 2
+; CHECK-LTO-NEXT: [[OR_641:%.*]] = or i16 [[OR_540]], [[STOREMERGE_6]]
+; CHECK-LTO-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds nuw i8, ptr [[DCT]], i64 14
+; CHECK-LTO-NEXT: [[TMP58:%.*]] = load i16, ptr [[ARRAYIDX_7]], align 2
+; CHECK-LTO-NEXT: [[CONV_7:%.*]] = sext i16 [[TMP58]] to i32
+; CHECK-LTO-NEXT: [[CMP1_7:%.*]] = icmp sgt i16 [[TMP58]], 0
+; CHECK-LTO-NEXT: [[ARRAYIDX4_7:%.*]] = getelementptr inbounds nuw i8, ptr [[BIAS]], i64 14
+; CHECK-LTO-NEXT: [[TMP59:%.*]] = load i16, ptr [[ARRAYIDX4_7]], align 2
+; CHECK-LTO-NEXT: [[CONV5_7:%.*]] = zext i16 [[TMP59]] to i32
+; CHECK-LTO-NEXT: [[ARRAYIDX10_7:%.*]] = getelementptr inbounds nuw i8, ptr [[MF]], i64 14
+; CHECK-LTO-NEXT: [[TMP60:%.*]] = load i16, ptr [[ARRAYIDX10_7]], align 2
+; CHECK-LTO-NEXT: [[CONV11_7:%.*]] = zext i16 [[TMP60]] to i32
+; CHECK-LTO-NEXT: br i1 [[CMP1_7]], label [[IF_THEN_7:%.*]], label [[IF_ELSE_7:%.*]]
+; CHECK-LTO: if.else.7:
+; CHECK-LTO-NEXT: [[ADD21_7:%.*]] = sub nsw i32 [[CONV5_7]], [[CONV_7]]
+; CHECK-LTO-NEXT: [[MUL25_7:%.*]] = mul i32 [[ADD21_7]], [[CONV11_7]]
+; CHECK-LTO-NEXT: [[SHR26_7:%.*]] = lshr i32 [[MUL25_7]...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/210088
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