[llvm] 0852ac5 - [PowerPC] Remove itinerary IIC_LdStDCBA (#207227)
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llvm-commits at lists.llvm.org
Thu Jul 16 07:55:17 PDT 2026
Author: Kai Nacke
Date: 2026-07-16T10:55:13-04:00
New Revision: 0852ac5649a0ac6959af6fbc2e4cf6cf4bad7238
URL: https://github.com/llvm/llvm-project/commit/0852ac5649a0ac6959af6fbc2e4cf6cf4bad7238
DIFF: https://github.com/llvm/llvm-project/commit/0852ac5649a0ac6959af6fbc2e4cf6cf4bad7238.diff
LOG: [PowerPC] Remove itinerary IIC_LdStDCBA (#207227)
The itinerary IIC_LdStDCBA is defined and used in scheduling models, but
no instruction is assigned to it. However, since the instruction is
basically retired (not part of the portable Power ISA), and all
scheduling models model it similar to IIC_LdStDCBF, the itinerary can be
removed.
Added:
Modified:
llvm/lib/Target/PowerPC/PPCSchedule.td
llvm/lib/Target/PowerPC/PPCSchedule440.td
llvm/lib/Target/PowerPC/PPCScheduleA2.td
llvm/lib/Target/PowerPC/PPCScheduleE500.td
llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
llvm/lib/Target/PowerPC/PPCScheduleE5500.td
llvm/lib/Target/PowerPC/PPCScheduleG3.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCSchedule.td b/llvm/lib/Target/PowerPC/PPCSchedule.td
index 81cb64e673628..aab8d972b63e6 100644
--- a/llvm/lib/Target/PowerPC/PPCSchedule.td
+++ b/llvm/lib/Target/PowerPC/PPCSchedule.td
@@ -34,7 +34,6 @@ def IIC_BrB : InstrItinClass;
def IIC_BrCR : InstrItinClass;
def IIC_BrMCR : InstrItinClass;
def IIC_BrMCRX : InstrItinClass;
-def IIC_LdStDCBA : InstrItinClass;
def IIC_LdStDCBF : InstrItinClass;
def IIC_LdStDCBI : InstrItinClass;
def IIC_LdStLoad : InstrItinClass;
diff --git a/llvm/lib/Target/PowerPC/PPCSchedule440.td b/llvm/lib/Target/PowerPC/PPCSchedule440.td
index 708261fc7cc8a..5fd1eae78de4b 100644
--- a/llvm/lib/Target/PowerPC/PPCSchedule440.td
+++ b/llvm/lib/Target/PowerPC/PPCSchedule440.td
@@ -230,13 +230,6 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [P440_IWB]>],
[4, 0, 0],
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
- InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
- InstrStage<1, [P440_LRACC]>,
- InstrStage<1, [P440_AGEN]>,
- InstrStage<1, [P440_CRD]>,
- InstrStage<1, [P440_LWB]>],
- [1, 1],
- [NoBypass, P440_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
InstrStage<1, [P440_LRACC]>,
InstrStage<1, [P440_AGEN]>,
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
index c2b298524e00a..955bdd32831f6 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
@@ -62,8 +62,6 @@ def PPCA2Itineraries : ProcessorItineraries<
[5, 0, 0]>,
InstrItinData<IIC_BrMCRX, [InstrStage<1, [A2_XU]>],
[1, 0, 0]>,
- InstrItinData<IIC_LdStDCBA, [InstrStage<1, [A2_XU]>],
- [1, 0, 0]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [A2_XU]>],
[1, 0, 0]>,
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [A2_XU]>],
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE500.td b/llvm/lib/Target/PowerPC/PPCScheduleE500.td
index 74744dda54f76..5a29925ca7ca3 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleE500.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleE500.td
@@ -111,10 +111,6 @@ def PPCE500Itineraries : ProcessorItineraries<
InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1
[E500_CR_Bypass, E500_GPR_Bypass]>,
- InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
- InstrStage<1, [E500_LSU_0]>],
- [6, 1], // Latency = 3, Repeat rate = 1
- [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
index 1a1c041565b67..960a6e4a57e89 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
@@ -124,10 +124,6 @@ def PPCE500mcItineraries : ProcessorItineraries<
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1
[E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
- InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
- InstrStage<1, [E500mc_LSU_0]>],
- [6, 1], // Latency = 3, Repeat rate = 1
- [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td
index 4480d7fba4fb8..f658469337a0c 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td
@@ -153,10 +153,6 @@ def PPCE5500Itineraries : ProcessorItineraries<
InstrStage<1, [E5500_CFX_0]>],
[5, 2, 2], // Latency = 1
[E5500_CR_Bypass, E5500_GPR_Bypass]>,
- InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
- InstrStage<1, [E5500_LSU_0]>],
- [7, 2], // Latency = 3, Repeat rate = 1
- [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
InstrStage<1, [E5500_LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG3.td b/llvm/lib/Target/PowerPC/PPCScheduleG3.td
index 8f1907f2c0163..f6b36500c3391 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleG3.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleG3.td
@@ -35,7 +35,6 @@ def G3Itineraries : ProcessorItineraries<
InstrItinData<IIC_BrCR , [InstrStage<1, [G3_SRU]>]>,
InstrItinData<IIC_BrMCR , [InstrStage<1, [G3_SRU]>]>,
InstrItinData<IIC_BrMCRX , [InstrStage<1, [G3_SRU]>]>,
- InstrItinData<IIC_LdStDCBA , [InstrStage<2, [G3_SLU]>]>,
InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G3_SLU]>]>,
InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G3_SLU]>]>,
InstrItinData<IIC_LdStLoad , [InstrStage<2, [G3_SLU]>]>,
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