[llvm] 6e7ff09 - [AMDGPU] Improve debug printing of regunits in SIInsertWaitcnts (#210066)
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Thu Jul 16 07:51:53 PDT 2026
Author: Jay Foad
Date: 2026-07-16T14:51:48Z
New Revision: 6e7ff09291652cc784a095707029852e249902f9
URL: https://github.com/llvm/llvm-project/commit/6e7ff09291652cc784a095707029852e249902f9
DIFF: https://github.com/llvm/llvm-project/commit/6e7ff09291652cc784a095707029852e249902f9.diff
LOG: [AMDGPU] Improve debug printing of regunits in SIInsertWaitcnts (#210066)
Use the standard printRegUnit helper.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index dad0d4f3dc353..87e204b3d29e8 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1143,7 +1143,8 @@ void WaitcntBrackets::print(raw_ostream &OS) const {
continue;
unsigned RelScore = RegScore - LB - 1;
if (ID < REGUNITS_END) {
- OS << ' ' << RelScore << ":vRU" << ID;
+ OS << ' ' << RelScore << ':'
+ << printRegUnit(static_cast<MCRegUnit>(ID), &Context->TRI);
} else {
assert(ID >= LDSDMA_BEGIN && ID < LDSDMA_END &&
"Unhandled/unexpected ID value!");
@@ -1160,7 +1161,8 @@ void WaitcntBrackets::print(raw_ostream &OS) const {
if (RegScore <= LB)
continue;
unsigned RelScore = RegScore - LB - 1;
- OS << ' ' << RelScore << ":sRU" << static_cast<unsigned>(ID);
+ OS << ' ' << RelScore << ':'
+ << printRegUnit(static_cast<MCRegUnit>(ID), &Context->TRI);
}
}
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