[llvm] 1cb7e83 - [AMDGPU] Simplify some isVALU calls. NFC. (#210057)

[via llvm-commits]

Author: Jay Foad
Date: 2026-07-16T15:32:20+01:00
New Revision: 1cb7e838cd47ecad4050948c0c907ecb1f466ac3

URL: https://github.com/llvm/llvm-project/commit/1cb7e838cd47ecad4050948c0c907ecb1f466ac3
DIFF: https://github.com/llvm/llvm-project/commit/1cb7e838cd47ecad4050948c0c907ecb1f466ac3.diff

LOG: [AMDGPU] Simplify some isVALU calls. NFC. (#210057)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
    llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
index 1b362aa8c8bd5..c6e5def726074 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
@@ -22,7 +22,7 @@ LLVM_DUMP_METHOD void HWEvents::dump() const { dbgs() << *this << "\n"; }
 
 static HWEvents getExpertSchedulingEventType(const MachineInstr &Inst,
                                              const SIInstrInfo &TII) {
-  if (TII.isVALU(Inst, /*AllowLDSDMA=*/true) && !SIInstrInfo::isLDSDMA(Inst)) {
+  if (TII.isVALU(Inst, /*AllowLDSDMA=*/false)) {
     // Core/Side-, DP-, XDL- and TRANS-MACC VALU instructions complete
     // out-of-order with respect to each other, so each of these classes
     // has its own event.

diff  --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 5996cdf42a956..dad0d4f3dc353 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -2498,7 +2498,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(
   // waits on VA_VDST if the instruction it would precede is not a VALU
   // instruction, since hardware handles VALU->VGPR->VALU hazards in
   // expert scheduling mode.
-  if (TII.isVALU(MI, /*AllowLDSDMA=*/true) && !SIInstrInfo::isLDSDMA(MI))
+  if (TII.isVALU(MI, /*AllowLDSDMA=*/false))
     Wait.set(AMDGPU::VA_VDST, ~0u);
 
   // Since the translation for VMEM addresses occur in-order, we can apply the