[llvm] [VectorCombine][X86] Add test coverage for #209714 (PR #210063)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/210063

None

>From 0a0046501ebb56dafe0eac501be6c2d44305dae1 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Thu, 16 Jul 2026 14:59:53 +0100
Subject: [PATCH] [VectorCombine][X86] Add test coverage for #209714

---
 .../X86/fold-signbit-reduction-cmp.ll         | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll b/llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
index 910e585e7b528..a7bbe290d8750 100644
--- a/llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
@@ -1219,5 +1219,31 @@ define i1 @negative_multi_op_mismatch(<4 x i32> %a, <4 x i32> %b) {
   %cmp = icmp eq i32 %red, 0
   ret i1 %cmp
 }
+
+; Hidden MOVMSK/TESTPS reduction pattern
+define i32 @PR209714(ptr %pa, ptr %pb) {
+; CHECK-LABEL: define i32 @PR209714(
+; CHECK-SAME: ptr [[PA:%.*]], ptr [[PB:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[A:%.*]] = load <2 x i64>, ptr [[PA]], align 16
+; CHECK-NEXT:    [[B:%.*]] = load <2 x i64>, ptr [[PB]], align 16
+; CHECK-NEXT:    [[A_NOT:%.*]] = xor <2 x i64> [[A]], splat (i64 -1)
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i64> [[B]], [[A_NOT]]
+; CHECK-NEXT:    [[AND_BC:%.*]] = bitcast <2 x i64> [[AND]] to <4 x i32>
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[AND_BC]])
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT:    [[RES:%.*]] = zext i1 [[CMP]] to i32
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %a = load <2 x i64>, ptr %pa, align 16
+  %b = load <2 x i64>, ptr %pb, align 16
+  %a.not = xor <2 x i64> %a, splat (i64 -1)
+  %and = and <2 x i64> %b, %a.not
+  %and.bc = bitcast <2 x i64> %and to <4 x i32>
+  %and.bc.sign = ashr <4 x i32> %and.bc, splat (i32 31)
+  %rdx = tail call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %and.bc.sign)
+  %cmp = icmp eq i32 %rdx, 0
+  %res = zext i1 %cmp to i32
+  ret i32 %res
+}
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; AVX: {{.*}}