[llvm] [RISCV][P-ext] Add packed sign and zero extend intrinsics (PR #208685)

[via llvm-commits]

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@@ -17771,6 +17839,29 @@ static SDValue combineNarrowableShiftedLoad(SDNode *N, SelectionDAG &DAG) {
                      DAG.getShiftAmountConstant(ShiftAmt, VT, DL));
 }
 
+static SDValue combinePZExt(SDNode *N, SelectionDAG &DAG,
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sihuan wrote:

Done in the last commit. `isVectorClearMaskLegal` enables `XformToShuffleWithZero`, and `lowerVECTOR_SHUFFLE` forms `PPAIRE` from the shuffle.

https://github.com/llvm/llvm-project/pull/208685