[llvm] [AMDGPU] Simplify some isVALU calls. NFC. (PR #210057)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 06:32:30 PDT 2026
https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/210057
None
>From 2b33bf8955d7f1b68b8d9b5d3e09661da7fab77e Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Thu, 16 Jul 2026 14:31:16 +0100
Subject: [PATCH] [AMDGPU] Simplify some isVALU calls. NFC.
---
llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
index 1b362aa8c8bd5..c6e5def726074 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHWEvents.cpp
@@ -22,7 +22,7 @@ LLVM_DUMP_METHOD void HWEvents::dump() const { dbgs() << *this << "\n"; }
static HWEvents getExpertSchedulingEventType(const MachineInstr &Inst,
const SIInstrInfo &TII) {
- if (TII.isVALU(Inst, /*AllowLDSDMA=*/true) && !SIInstrInfo::isLDSDMA(Inst)) {
+ if (TII.isVALU(Inst, /*AllowLDSDMA=*/false)) {
// Core/Side-, DP-, XDL- and TRANS-MACC VALU instructions complete
// out-of-order with respect to each other, so each of these classes
// has its own event.
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 5996cdf42a956..dad0d4f3dc353 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -2498,7 +2498,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(
// waits on VA_VDST if the instruction it would precede is not a VALU
// instruction, since hardware handles VALU->VGPR->VALU hazards in
// expert scheduling mode.
- if (TII.isVALU(MI, /*AllowLDSDMA=*/true) && !SIInstrInfo::isLDSDMA(MI))
+ if (TII.isVALU(MI, /*AllowLDSDMA=*/false))
Wait.set(AMDGPU::VA_VDST, ~0u);
// Since the translation for VMEM addresses occur in-order, we can apply the
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