[llvm] [PPC] Constrain register in VSPLT of XXSLDWI transform (PR #208005)

[Nikita Popov via llvm-commits]

https://github.com/nikic updated https://github.com/llvm/llvm-project/pull/208005

>From e31a099de2540c929686eb21a9903aa1a941ccca Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Tue, 7 Jul 2026 15:58:52 +0200
Subject: [PATCH 1/2] [PPC] Constrain register in VSPLT of XXSLDWI transform

XXSLDWI takes a vsrc register, but the VSPLT opcodes only take
vrrc. vrrc is a subset of vsrc, so fix this by constraining the
register class.
---
 llvm/lib/Target/PowerPC/PPCMIPeephole.cpp     |  2 ++
 .../CodeGen/PowerPC/splat-after-xxsldwi.ll    | 21 +++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 20df2210e33dd..5ca7e1d8fad6f 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -889,6 +889,8 @@ bool PPCMIPeephole::simplifyCode() {
             LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm
                               << " to " << NewElem << " in instruction: ");
             LLVM_DEBUG(MI.dump());
+            if (!MRI->constrainRegClass(ShiftOp1, &PPC::VRRCRegClass))
+              llvm_unreachable("vrrc is subset of vsrc");
             addRegToUpdate(MI.getOperand(OpNo).getReg());
             addRegToUpdate(ShiftOp1);
             MI.getOperand(OpNo).setReg(ShiftOp1);
diff --git a/llvm/test/CodeGen/PowerPC/splat-after-xxsldwi.ll b/llvm/test/CodeGen/PowerPC/splat-after-xxsldwi.ll
index 9790ec1b6bf72..d9d7e64e293aa 100644
--- a/llvm/test/CodeGen/PowerPC/splat-after-xxsldwi.ll
+++ b/llvm/test/CodeGen/PowerPC/splat-after-xxsldwi.ll
@@ -20,3 +20,24 @@ entry:
   %foldExtExtBinop = and <4 x i8> %shift, %conv4
   ret <4 x i8> %foldExtExtBinop
 }
+
+define <4 x i8> @backsmith_pure_load(ptr %p) {
+; CHECK-LABEL: backsmith_pure_load:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi r3, r3, 16
+; CHECK-NEXT:    lxvw4x vs34, 0, r3
+; CHECK-NEXT:    ld r3, L..C1(r2) # %const.0
+; CHECK-NEXT:    lxvw4x vs36, 0, r3
+; CHECK-NEXT:    xxsldwi vs35, vs34, vs34, 1
+; CHECK-NEXT:    vspltb v2, v2, 3
+; CHECK-NEXT:    vperm v3, v3, v3, v4
+; CHECK-NEXT:    xxland vs34, vs34, vs35
+; CHECK-NEXT:    blr
+entry:
+  %v = load <8 x i32>, ptr %p
+  %shuffle = shufflevector <8 x i32> %v, <8 x i32> zeroinitializer, <4 x i32> <i32 5, i32 6, i32 7, i32 4>
+  %conv4 = trunc <4 x i32> %shuffle to <4 x i8>
+  %shift = shufflevector <4 x i8> %conv4, <4 x i8> zeroinitializer, <4 x i32> <i32 3, i32 poison, i32 poison, i32 poison>
+  %foldExtExtBinop = and <4 x i8> %shift, %conv4
+  ret <4 x i8> %foldExtExtBinop
+}

>From 5372f829075766845c8986e34db921bb94f9db49 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Thu, 16 Jul 2026 14:42:45 +0200
Subject: [PATCH 2/2] Clarify message

---
 llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 5ca7e1d8fad6f..f47cb785b8588 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -890,7 +890,7 @@ bool PPCMIPeephole::simplifyCode() {
                               << " to " << NewElem << " in instruction: ");
             LLVM_DEBUG(MI.dump());
             if (!MRI->constrainRegClass(ShiftOp1, &PPC::VRRCRegClass))
-              llvm_unreachable("vrrc is subset of vsrc");
+              llvm_unreachable("Can't fail because vrrc is subset of vsrc");
             addRegToUpdate(MI.getOperand(OpNo).getReg());
             addRegToUpdate(ShiftOp1);
             MI.getOperand(OpNo).setReg(ShiftOp1);