[llvm] [AArch64] SME definitions for C1-Nano scheduling model (PR #207174)

[via llvm-commits]

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@@ -1382,176 +1629,218 @@ def : InstRW<[C1NanoWrite_68c_1VMC_66rc],
 
 
 // Bitwise select
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+                                        C1NanoWrite_3c_1VALU>],
              (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>;
 
 // Count/reverse bits
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+                                        C1NanoWrite_3c_1VALU>],
              (instregex "^(CLS|CLZ|RBIT)_ZPmZ_[BHSD]")>;
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+                                        C1NanoWrite_3c_1VALU>],
              (instregex "^CNT_ZPmZ_[BH]")>;
-def : InstRW<[C1NanoWrite_6c_2VALU_4rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+                                        C1NanoWrite_6c_2VALU_4rc>],
              (instregex "^CNT_ZPmZ_S")>;
-def : InstRW<[C1NanoWrite_9c_2VALU_7rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+                                        C1NanoWrite_9c_2VALU_7rc>],
              (instregex "^CNT_ZPmZ_D")>;
 // Broadcast logical bitmask immediate to vector.
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+                                        C1NanoWrite_4c_1VALU>],
              (instrs DUPM_ZI)>;
 
 // Compare and set flags
-def : InstRW<[C1NanoWrite_5c_2VALU_1rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVX0ALU,
+                                        C1NanoWrite_5c_2VALU_1rc>],
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walkerkd wrote:

Fixed

https://github.com/llvm/llvm-project/pull/207174