[llvm] [VPlan] Expand affine AddRecs to VPInstructions (PR #209921)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 04:23:41 PDT 2026
https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/209921
>From f6b5b544b4e40f880fd2fab5243b0d9c21e5cce5 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Wed, 15 Jul 2026 21:03:07 +0100
Subject: [PATCH 1/2] [LV] Pe-commit test iv-start-addrec
---
.../LoopVectorize/VPlan/expand-scev.ll | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
index 1e55658ce19ae..5536d6dff28c3 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -357,6 +357,46 @@ exit:
ret void
}
+define void @iv_start_is_addrec(ptr %start, ptr %end) {
+; CHECK-LABEL: VPlan for loop in 'iv_start_is_addrec'
+; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
+; CHECK-NEXT: Live-in ir<%10> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<ph>:
+; CHECK-NEXT: IR %ind.incoming = phi i64 [ 0, %entry ], [ %ind.incoming.next, %exit ]
+; CHECK-NEXT: IR %7 = mul i64 %ind.incoming, -9223372036854775804
+; CHECK-NEXT: IR %8 = add i64 %6, %7
+; CHECK-NEXT: IR %9 = lshr i64 %8, 3
+; CHECK-NEXT: IR %10 = add nuw nsw i64 %9, 1
+; CHECK-NEXT: IR %11 = mul i64 %ind.incoming, -4
+; CHECK-NEXT: IR %12 = add i64 %3, %11
+; CHECK-NEXT: IR %13 = trunc i64 %12 to i3
+; CHECK-NEXT: IR %14 = zext i3 %13 to i64
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%10>, ir<4>
+; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
+; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.scevcheck>
+;
+entry:
+ br label %ph
+
+ph:
+ %ind.incoming = phi i64 [ 0, %entry ], [ %ind.incoming.next, %exit ]
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %ph ], [ %iv.next, %loop ]
+ %ind = phi i64 [ %ind.incoming, %ph ], [ %ind.next, %loop ]
+ %ind.next = add i64 %ind, -2
+ %start.ind = getelementptr [4 x i8], ptr %start, i64 %ind
+ %iv.next = add i64 %iv, 1
+ %ec = icmp ne ptr %start.ind, %end
+ br i1 %ec, label %loop, label %exit
+
+exit:
+ %ind.incoming.next = add i64 %ind.incoming, 1
+ br label %ph
+}
+
!0 = distinct !{!0, !1, !2}
!1 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
>From 3af4083d8a92c224cce1783e6ccc9d4f796ae44d Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Wed, 15 Jul 2026 22:14:03 +0100
Subject: [PATCH 2/2] [VPlan] Expand affine AddRecs to VPInstructions
Extend VPSCEVExpander to handle affine AddRecs, under the condition that
a canonical IV phi is already present. The patch has necessitated fixing
underlying issues in VPIRInstruction.
Co-authored-by: Florian Hahn <flo at fhahn.com>
---
llvm/lib/Transforms/Vectorize/VPlan.cpp | 5 +-
llvm/lib/Transforms/Vectorize/VPlan.h | 16 +++----
.../lib/Transforms/Vectorize/VPlanRecipes.cpp | 3 +-
.../Transforms/Vectorize/VPlanTransforms.cpp | 2 +-
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp | 48 +++++++++++++++++++
.../LoopVectorize/RISCV/strided-accesses.ll | 8 ++--
.../LoopVectorize/VPlan/expand-scev.ll | 33 +++++++------
.../nested-loops-scev-expansion.ll | 3 +-
.../pr55100-expand-scev-predicate-used.ll | 6 +--
.../reuse-lcssa-phi-scev-expansion.ll | 10 ++--
10 files changed, 92 insertions(+), 42 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index 7d69b3453cba9..8a4fca5f5f421 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -279,7 +279,7 @@ VPTransformState::VPTransformState(const TargetTransformInfo *TTI,
CurrentParentLoop(CurrentParentLoop), VPDT(*Plan) {}
Value *VPTransformState::get(const VPValue *Def, const VPLane &Lane) {
- if (isa<VPIRValue, VPSymbolicValue>(Def))
+ if (isa<VPIRValue, VPSymbolicValue, VPIRInstruction>(Def))
return Def->getUnderlyingValue();
if (hasScalarValue(Def, Lane))
@@ -312,7 +312,8 @@ Value *VPTransformState::get(const VPValue *Def, const VPLane &Lane) {
Value *VPTransformState::get(const VPValue *Def, bool NeedsScalar) {
if (NeedsScalar) {
- assert((VF.isScalar() || isa<VPIRValue, VPSymbolicValue>(Def) ||
+ assert((VF.isScalar() ||
+ isa<VPIRValue, VPSymbolicValue, VPIRInstruction>(Def) ||
hasVectorValue(Def) || !vputils::onlyFirstLaneUsed(Def) ||
(hasScalarValue(Def, VPLane(0)) &&
Data.VPV2Scalars[Def].size() == 1)) &&
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index b67d1a1281c14..3fd627cb2a023 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1716,14 +1716,14 @@ struct LLVM_ABI_FOR_TEST VPPhi : public VPInstruction, public VPPhiAccessors {
/// A recipe to wrap on original IR instruction not to be modified during
/// execution, except for PHIs. PHIs are modeled via the VPIRPhi subclass.
/// Expect PHIs, VPIRInstructions cannot have any operands.
-class VPIRInstruction : public VPRecipeBase {
- Instruction &I;
-
+class VPIRInstruction : public VPSingleDefRecipe {
protected:
/// VPIRInstruction::create() should be used to create VPIRInstructions, as
/// subclasses may need to be created, e.g. VPIRPhi.
VPIRInstruction(Instruction &I)
- : VPRecipeBase(VPRecipeBase::VPIRInstructionSC, {}), I(I) {}
+ : VPSingleDefRecipe(VPRecipeBase::VPIRInstructionSC, {}, I.getType()) {
+ setUnderlyingValue(&I);
+ }
public:
~VPIRInstruction() override = default;
@@ -1735,7 +1735,7 @@ class VPIRInstruction : public VPRecipeBase {
VP_CLASSOF_IMPL(VPRecipeBase::VPIRInstructionSC)
VPIRInstruction *clone() override {
- auto *R = create(I);
+ auto *R = create(*getUnderlyingInstr());
for (auto *Op : operands())
R->addOperand(Op);
return R;
@@ -1747,8 +1747,6 @@ class VPIRInstruction : public VPRecipeBase {
LLVM_ABI_FOR_TEST InstructionCost
computeCost(ElementCount VF, VPCostContext &Ctx) const override;
- Instruction &getInstruction() const { return I; }
-
bool usesScalars(const VPValue *Op) const override {
assert(is_contained(operands(), Op) &&
"Op must be an operand of the recipe");
@@ -1785,7 +1783,7 @@ struct LLVM_ABI_FOR_TEST VPIRPhi : public VPIRInstruction,
static inline bool classof(const VPRecipeBase *U) {
auto *R = dyn_cast<VPIRInstruction>(U);
- return R && isa<PHINode>(R->getInstruction());
+ return R && isa<PHINode>(R->getUnderlyingInstr());
}
static inline bool classof(const VPUser *U) {
@@ -1793,7 +1791,7 @@ struct LLVM_ABI_FOR_TEST VPIRPhi : public VPIRInstruction,
return R && classof(R);
}
- PHINode &getIRPhi() { return cast<PHINode>(getInstruction()); }
+ PHINode &getIRPhi() { return cast<PHINode>(*getUnderlyingInstr()); }
void execute(VPTransformState &State) override;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index 3fbeb7e772a2e..b6df22c46efa2 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -2008,6 +2008,7 @@ void VPIRInstruction::execute(VPTransformState &State) {
"PHINodes must be handled by VPIRPhi");
// Advance the insert point after the wrapped IR instruction. This allows
// interleaving VPIRInstructions and other recipes.
+ Instruction &I = *getUnderlyingInstr();
State.Builder.SetInsertPoint(I.getParent(), std::next(I.getIterator()));
}
@@ -2021,7 +2022,7 @@ InstructionCost VPIRInstruction::computeCost(ElementCount VF,
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
void VPIRInstruction::printRecipe(raw_ostream &O, const Twine &Indent,
VPSlotTracker &SlotTracker) const {
- O << Indent << "IR " << I;
+ O << Indent << "IR " << *getUnderlyingInstr();
}
#endif
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 47e51f9639903..a432acc04b4aa 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -5854,7 +5854,7 @@ VPlanTransforms::expandSCEVs(VPlan &Plan, ScalarEvolution &SE) {
auto EI = Entry->begin();
for (Instruction &I : drop_end(*EntryBB)) {
if (EI != Entry->end() && isa<VPIRInstruction>(*EI) &&
- &cast<VPIRInstruction>(&*EI)->getInstruction() == &I) {
+ cast<VPIRInstruction>(&*EI)->getUnderlyingInstr() == &I) {
EI++;
continue;
}
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index 03e1ead89c169..c4e8ac1cf0c48 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -13,6 +13,7 @@
#include "VPlanDominatorTree.h"
#include "VPlanPatternMatch.h"
#include "llvm/ADT/TypeSwitch.h"
+#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/Analysis/ScalarEvolutionPatternMatch.h"
@@ -888,6 +889,53 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
ResultTy, DL);
return Result;
}
+ case scAddRecExpr: {
+ auto *AR = cast<SCEVAddRecExpr>(S);
+ // Find a canonical IV to re-use. AddRecs never appear in the vector loop;
+ // the AR's loop would correspond to an outer loop outside the vector loop,
+ // modeled as a VPIRBasicBlock.
+ PHINode *CanIVPhi = AR->getLoop()->getCanonicalInductionVariable();
+ VPValue *CanonicalIV = nullptr;
+ for (auto *VPBB : VPBlockUtils::blocksOnly<VPIRBasicBlock>(
+ vp_depth_first_shallow(Builder.getPlan().getEntry())))
+ for (VPRecipeBase &R : *VPBB)
+ if (auto *IRPhi = dyn_cast<VPIRPhi>(&R))
+ if (&IRPhi->getIRPhi() == CanIVPhi) {
+ CanonicalIV = IRPhi;
+ break;
+ }
+
+ // Since the AddRec's loop is not modeled in Plan, and because it is
+ // impossible to map back from the AddRec's loop header to a VPBB in the
+ // Plan, we can only expand the AddRecs to VPInstructions when we can safely
+ // re-use a canonical induction variable that is already identically present
+ // in the Plan.
+ if (!CanonicalIV)
+ return vputils::getOrCreateVPValueForSCEVExpr(Builder.getPlan(), AR);
+
+ VPValue *Start;
+ Start = tryToExpand(AR->getStart());
+ if (!Start)
+ return nullptr;
+ VPValue *Step = tryToExpand(AR->getStepRecurrence(SE));
+ if (!Step)
+ return nullptr;
+
+ GEPNoWrapFlags GEPFlags;
+ VPIRFlags::WrapFlagsTy NWFlags;
+ if (AR->hasNoUnsignedWrap()) {
+ GEPFlags = GEPNoWrapFlags::noUnsignedSignedWrap();
+ NWFlags = {true, false};
+ }
+
+ // {X,+,F} --> X + {0,+,F}
+ // {0,+,F} --> {0,+,1} * F
+ VPValue *Offset = Builder.createOverflowingOp(Instruction::Mul,
+ {CanonicalIV, Step}, NWFlags);
+ return AR->getType()->isPointerTy()
+ ? Builder.createNoWrapPtrAdd(Start, Offset, GEPFlags, DL)
+ : Builder.createAdd(Start, Offset, DL, "", NWFlags);
+ }
default:
return nullptr;
}
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
index 1062ba477bdce..83aacd6139668 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
@@ -2146,10 +2146,10 @@ define void @iv_start_is_addrec(ptr %p, ptr noalias %q) {
; CHECK-NEXT: br label %[[PH:.*]]
; CHECK: [[PH]]:
; CHECK-NEXT: [[IND_INCOMING:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IND_INCOMING_NEXT:%.*]], %[[EXIT:.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IND_INCOMING]], 2
-; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP0]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IND_INCOMING]], 2
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP0]]
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[Q]], i64 0
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
@@ -2178,8 +2178,6 @@ define void @iv_start_is_addrec(ptr %p, ptr noalias %q) {
; CHECK-UF2-NEXT: br label %[[PH:.*]]
; CHECK-UF2: [[PH]]:
; CHECK-UF2-NEXT: [[IND_INCOMING:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IND_INCOMING_NEXT:%.*]], %[[EXIT:.*]] ]
-; CHECK-UF2-NEXT: [[TMP6:%.*]] = shl i64 [[IND_INCOMING]], 2
-; CHECK-UF2-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP6]]
; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 5
; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 129, [[TMP1]]
@@ -2192,6 +2190,8 @@ define void @iv_start_is_addrec(ptr %p, ptr noalias %q) {
; CHECK-UF2-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], -2
; CHECK-UF2-NEXT: [[TMP5:%.*]] = add i64 [[IND_INCOMING]], [[TMP4]]
; CHECK-UF2-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP2]] to i32
+; CHECK-UF2-NEXT: [[TMP17:%.*]] = shl i64 [[IND_INCOMING]], 2
+; CHECK-UF2-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP17]]
; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-UF2: [[VECTOR_BODY]]:
; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
index 5536d6dff28c3..8b39730ebe570 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -321,14 +321,13 @@ exit:
define void @scev_addrec_expanded(ptr %dst) {
; CHECK-LABEL: VPlan for loop in 'scev_addrec_expanded'
; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
-; CHECK-NEXT: Live-in ir<%2> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<outer>:
; CHECK-NEXT: IR %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
-; CHECK-NEXT: IR %0 = add i64 %outer.iv, 4
-; CHECK-NEXT: IR %1 = udiv i64 %0, 3
-; CHECK-NEXT: IR %2 = add nuw nsw i64 %1, 1
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%2>, ir<4>
+; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = add nuw ir<4>, ir<%outer.iv>.1
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = udiv vp<[[VP2]]>, ir<3>
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = add nuw nsw vp<[[VP3]]>, ir<1>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP4]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
;
@@ -360,19 +359,23 @@ exit:
define void @iv_start_is_addrec(ptr %start, ptr %end) {
; CHECK-LABEL: VPlan for loop in 'iv_start_is_addrec'
; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
-; CHECK-NEXT: Live-in ir<%10> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<ph>:
; CHECK-NEXT: IR %ind.incoming = phi i64 [ 0, %entry ], [ %ind.incoming.next, %exit ]
-; CHECK-NEXT: IR %7 = mul i64 %ind.incoming, -9223372036854775804
-; CHECK-NEXT: IR %8 = add i64 %6, %7
-; CHECK-NEXT: IR %9 = lshr i64 %8, 3
-; CHECK-NEXT: IR %10 = add nuw nsw i64 %9, 1
-; CHECK-NEXT: IR %11 = mul i64 %ind.incoming, -4
-; CHECK-NEXT: IR %12 = add i64 %3, %11
-; CHECK-NEXT: IR %13 = trunc i64 %12 to i3
-; CHECK-NEXT: IR %14 = zext i3 %13 to i64
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%10>, ir<4>
+; CHECK-NEXT: IR %4 = mul i64 %ind.incoming, -4
+; CHECK-NEXT: IR %5 = add i64 %3, %4
+; CHECK-NEXT: IR %6 = trunc i64 %5 to i3
+; CHECK-NEXT: IR %7 = zext i3 %6 to i64
+; CHECK-NEXT: EMIT-SCALAR vp<[[VP2:%[0-9]+]]> = ptrtoint ir<%start> to i64
+; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = mul vp<[[VP2]]>, ir<-2305843009213693951>
+; CHECK-NEXT: EMIT-SCALAR vp<[[VP4:%[0-9]+]]> = ptrtoint ir<%end> to i64
+; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = mul vp<[[VP4]]>, ir<2305843009213693951>
+; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = add vp<[[VP3]]>, vp<[[VP5]]>
+; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = mul ir<%ind.incoming>.1, ir<-9223372036854775804>
+; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = add vp<[[VP6]]>, vp<[[VP7]]>
+; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = lshr vp<[[VP8]]>, ir<3>
+; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = add nuw nsw vp<[[VP9]]>, ir<1>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP10]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.scevcheck>
;
diff --git a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
index 491882b796ef1..a6f6992b963e5 100644
--- a/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
+++ b/llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
@@ -339,9 +339,8 @@ define void @test_expand_secv_in_entry_before_gep(ptr %dst) {
; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
; CHECK: [[OUTER_HEADER]]:
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[OUTER_IV_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[OUTER_IV]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 112
; CHECK-NEXT: [[GEP_M:%.*]] = getelementptr [36 x [36 x double]], ptr [[DST]], i64 0, i64 [[OUTER_IV]]
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 112, [[OUTER_IV]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/pr55100-expand-scev-predicate-used.ll b/llvm/test/Transforms/LoopVectorize/pr55100-expand-scev-predicate-used.ll
index d3b8dafaf0002..899c4223db07d 100644
--- a/llvm/test/Transforms/LoopVectorize/pr55100-expand-scev-predicate-used.ll
+++ b/llvm/test/Transforms/LoopVectorize/pr55100-expand-scev-predicate-used.ll
@@ -10,11 +10,11 @@ define void @test_pr55100(i32 %N) {
; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_1_NEXT:%.*]], [[LOOP_1_LATCH:%.*]] ]
; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[IV_1]], -1
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[UMIN:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP2]], i32 18)
-; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[UMIN]], 1
; CHECK-NEXT: [[C_2:%.*]] = icmp ugt i32 [[IV_1]], 10
; CHECK-NEXT: br i1 [[C_2]], label [[LOOP_2_HEADER_PREHEADER:%.*]], label [[EXIT_LOOPEXIT1:%.*]]
; CHECK: loop.2.header.preheader:
+; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP2]], i32 18)
+; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP7]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP3]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
@@ -44,7 +44,7 @@ define void @test_pr55100(i32 %N) {
; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[ADD_1]], [[IV_2_EXT]]
; CHECK-NEXT: [[C_4:%.*]] = icmp ult i32 [[ADD_2]], 1
; CHECK-NEXT: [[IV_2_NEXT]] = add i16 [[IV_2]], 1
-; CHECK-NEXT: br i1 [[C_4]], label [[EXIT_LOOPEXIT:%.*]], label [[LOOP_2_HEADER]], !llvm.loop [[LOOP2:![0-9]+]]
+; CHECK-NEXT: br i1 [[C_4]], label [[EXIT_LOOPEXIT:%.*]], label [[LOOP_2_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: loop.1.latch:
; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1
; CHECK-NEXT: br label [[LOOP_1_HEADER]]
diff --git a/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
index 26f7fc23d7ef7..1e79ddf81cfb0 100644
--- a/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
+++ b/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
@@ -19,7 +19,7 @@ define void @reuse_lcssa_phi_for_add_rec1(ptr %head) {
; CHECK-NEXT: br i1 [[EC_1]], label %[[PH:.*]], label %[[LOOP_1]]
; CHECK: [[PH]]:
; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], %[[LOOP_1]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[IV_2_NEXT]], %[[LOOP_1]] ]
+; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_2_NEXT]], %[[LOOP_1]] ]
; CHECK-NEXT: [[SRC_2:%.*]] = tail call noalias noundef dereferenceable_or_null(8) ptr @calloc(i64 1, i64 8)
; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[IV_2_NEXT]], i32 1)
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[IV_2_NEXT]], [[SMIN]]
@@ -206,12 +206,10 @@ define void @expand_diff_scev_unknown(ptr %dst, i1 %invar.c, i32 %step) mustprog
; CHECK-NEXT: br i1 [[INVAR_C]], label %[[LOOP_2_PREHEADER:.*]], label %[[LOOP_1]]
; CHECK: [[LOOP_2_PREHEADER]]:
; CHECK-NEXT: [[IV_1_LCSSA:%.*]] = phi i32 [ [[IV_1]], %[[LOOP_1]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = sub i32 2, [[STEP]]
-; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[IV_1_LCSSA]], [[TMP0]]
-; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP12]], i32 0)
; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[INDVAR]], -1
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP3]], -1
-; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[SMAX1]], [[TMP14]]
+; CHECK-NEXT: [[TMP16:%.*]] = sub i32 2, [[STEP]]
+; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[IV_1_LCSSA]], [[TMP16]]
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[IV_1_LCSSA]], [[STEP]]
; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 0)
; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[STEP]], -2
@@ -223,6 +221,8 @@ define void @expand_diff_scev_unknown(ptr %dst, i1 %invar.c, i32 %step) mustprog
; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[STEP]], i32 1)
; CHECK-NEXT: [[TMP8:%.*]] = udiv i32 [[TMP7]], [[UMAX]]
; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[TMP6]], [[TMP8]]
+; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP17]], i32 0)
+; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP12]], [[TMP14]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP15]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
More information about the llvm-commits
mailing list