[llvm] [ConstraintElim] Handle (X | Y) >s -1 as X >s -1 && Y >s -1. (PR #209743)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 04:04:15 PDT 2026
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/209743
>From 778b87e462b9ed81c916d979ec26077b02ea3f10 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Tue, 14 Jul 2026 19:24:46 +0100
Subject: [PATCH 1/3] [ConstraintElim] Handle (X | Y) >=s 0 as X >=s 0 && Y >=s
0.
InstCombine canonicalizes X >=s 0 && Y >=s 0 as (X | Y) >=s 0. Teach
ConstraintElimination to recover the signed-positive information by
looking through compares of binary ORs.
Alive2 Proof: https://alive2.llvm.org/ce/z/ACu4gs
---
.../Scalar/ConstraintElimination.cpp | 24 +++++++++++++++++++
.../ConstraintElimination/or-non-negative.ll | 9 +++----
.../constraint-eliminiation-interactions.ll | 12 +++-------
3 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
index b244445c6e51f..5c064751956e2 100644
--- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
@@ -1996,6 +1996,30 @@ static bool eliminateConstraints(Function &F, DominatorTree &DT, LoopInfo &LI,
DFSInStack);
}
+ // (X | Y) >=s 0 implies X >=s 0 and Y >=s 0, because the sign bit of an
+ // OR is the OR of the operand sign bits. Look through this
+ // canonicalization by InstCombine. disjunct so it is available to the
+ // solver.
+ if ((Pred == CmpInst::ICMP_SGE && match(B, m_Zero())) ||
+ (Pred == CmpInst::ICMP_SGT && match(B, m_AllOnes()))) {
+ SmallVector<Value *> OrWorklist = {A};
+ SmallPtrSet<Value *, 4> SeenOr;
+ Value *X, *Y;
+ while (!OrWorklist.empty()) {
+ Value *Cur = OrWorklist.pop_back_val();
+ if (!match(Cur, m_Or(m_Value(X), m_Value(Y))))
+ continue;
+ for (Value *Op : {X, Y}) {
+ if (!SeenOr.insert(Op).second)
+ continue;
+ OrWorklist.push_back(Op);
+ Info.addFact(CmpInst::ICMP_SGE, Op,
+ ConstantInt::getNullValue(Op->getType()), CB.NumIn,
+ CB.NumOut, DFSInStack);
+ }
+ }
+ }
+
if (ReproducerModule && DFSInStack.size() > ReproducerCondStack.size()) {
// Add dummy entries to ReproducerCondStack to keep it in sync with
// DFSInStack.
diff --git a/llvm/test/Transforms/ConstraintElimination/or-non-negative.ll b/llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
index b8413acbbf2cf..92b80e5459499 100644
--- a/llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
+++ b/llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
@@ -17,8 +17,7 @@ define i1 @or_non_negative_bounds(i64 %a, i64 %b, i64 %c, i64 %d) {
; CHECK-NEXT: br i1 [[AND_3]], label %[[THEN:.*]], label %[[ELSE:.*]]
; CHECK: [[THEN]]:
; CHECK-NEXT: [[IDX:%.*]] = add nsw i64 [[D]], [[B]]
-; CHECK-NEXT: [[RES:%.*]] = icmp ult i64 [[IDX]], [[A]]
-; CHECK-NEXT: ret i1 [[RES]]
+; CHECK-NEXT: ret i1 true
; CHECK: [[ELSE]]:
; CHECK-NEXT: ret i1 false
;
@@ -50,8 +49,7 @@ define i1 @or_non_negative_sge(i64 %a, i64 %b) {
; CHECK-NEXT: [[C:%.*]] = icmp sge i64 [[O]], 0
; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[ELSE:.*]]
; CHECK: [[THEN]]:
-; CHECK-NEXT: [[RES:%.*]] = icmp sge i64 [[B]], 0
-; CHECK-NEXT: ret i1 [[RES]]
+; CHECK-NEXT: ret i1 true
; CHECK: [[ELSE]]:
; CHECK-NEXT: ret i1 false
;
@@ -76,8 +74,7 @@ define i1 @or_non_negative_nested(i64 %a, i64 %b, i64 %c) {
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[O2]], -1
; CHECK-NEXT: br i1 [[CMP]], label %[[THEN:.*]], label %[[ELSE:.*]]
; CHECK: [[THEN]]:
-; CHECK-NEXT: [[RES:%.*]] = icmp sge i64 [[C]], 0
-; CHECK-NEXT: ret i1 [[RES]]
+; CHECK-NEXT: ret i1 true
; CHECK: [[ELSE]]:
; CHECK-NEXT: ret i1 false
;
diff --git a/llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll b/llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
index a5a1fcb97541a..375649d8790e9 100644
--- a/llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
+++ b/llvm/test/Transforms/PhaseOrdering/constraint-eliminiation-interactions.ll
@@ -70,16 +70,10 @@ define noundef i64 @or_sge_canonicalization(ptr noundef %p, i64 noundef %a, i64
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i64 [[TMP1]], -1
; CHECK-NEXT: [[AND_3:%.*]] = and i1 [[CMP_3]], [[TMP2]]
; CHECK-NEXT: [[AND_4:%.*]] = and i1 [[CMP_5]], [[AND_3]]
-; CHECK-NEXT: br i1 [[AND_4]], label %[[THEN:.*]], label %[[ELSE:.*]]
-; CHECK: [[THEN]]:
-; CHECK-NEXT: [[IDX:%.*]] = add nuw nsw i64 [[D]], [[B]]
-; CHECK-NEXT: [[OOB_NOT:%.*]] = icmp ult i64 [[IDX]], [[A]]
-; CHECK-NEXT: br i1 [[OOB_NOT]], label %[[CONT:.*]], label %[[TRAP:.*]]
-; CHECK: [[TRAP]]:
-; CHECK-NEXT: tail call void @llvm.trap()
-; CHECK-NEXT: unreachable
+; CHECK-NEXT: br i1 [[AND_4]], label %[[CONT:.*]], label %[[ELSE:.*]]
; CHECK: [[CONT]]:
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [8 x i8], ptr [[P]], i64 [[IDX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [8 x i8], ptr [[P]], i64 [[D]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [8 x i8], ptr [[TMP3]], i64 [[B]]
; CHECK-NEXT: [[V:%.*]] = load i64, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT: br label %[[ELSE]]
; CHECK: [[ELSE]]:
>From 0bdf09572d4e80426b66e00ea4c0e365258531f2 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Wed, 15 Jul 2026 14:50:53 +0100
Subject: [PATCH 2/3] !fixup strip stray comment, remove sge 0 support
---
llvm/lib/Transforms/Scalar/ConstraintElimination.cpp | 8 +++-----
.../Transforms/ConstraintElimination/or-non-negative.ll | 3 ++-
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
index 5c064751956e2..12a0792fd4148 100644
--- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
@@ -1996,12 +1996,10 @@ static bool eliminateConstraints(Function &F, DominatorTree &DT, LoopInfo &LI,
DFSInStack);
}
- // (X | Y) >=s 0 implies X >=s 0 and Y >=s 0, because the sign bit of an
+ // (X | Y) >s -1 implies X >s -1 and Y >s -1, because the sign bit of an
// OR is the OR of the operand sign bits. Look through this
- // canonicalization by InstCombine. disjunct so it is available to the
- // solver.
- if ((Pred == CmpInst::ICMP_SGE && match(B, m_Zero())) ||
- (Pred == CmpInst::ICMP_SGT && match(B, m_AllOnes()))) {
+ // canonicalization by InstCombine.
+ if (Pred == CmpInst::ICMP_SGT && match(B, m_AllOnes())) {
SmallVector<Value *> OrWorklist = {A};
SmallPtrSet<Value *, 4> SeenOr;
Value *X, *Y;
diff --git a/llvm/test/Transforms/ConstraintElimination/or-non-negative.ll b/llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
index 92b80e5459499..138ea41198b91 100644
--- a/llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
+++ b/llvm/test/Transforms/ConstraintElimination/or-non-negative.ll
@@ -49,7 +49,8 @@ define i1 @or_non_negative_sge(i64 %a, i64 %b) {
; CHECK-NEXT: [[C:%.*]] = icmp sge i64 [[O]], 0
; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[ELSE:.*]]
; CHECK: [[THEN]]:
-; CHECK-NEXT: ret i1 true
+; CHECK-NEXT: [[RES:%.*]] = icmp sge i64 [[B]], 0
+; CHECK-NEXT: ret i1 [[RES]]
; CHECK: [[ELSE]]:
; CHECK-NEXT: ret i1 false
;
>From a2aa4cacb953b32d6319939b9aee3226a7294334 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Thu, 16 Jul 2026 11:58:29 +0100
Subject: [PATCH 3/3] !fixup use Pred instead of spelling out predicate.
---
llvm/lib/Transforms/Scalar/ConstraintElimination.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
index 12a0792fd4148..f1f800cd69d60 100644
--- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
@@ -2011,9 +2011,7 @@ static bool eliminateConstraints(Function &F, DominatorTree &DT, LoopInfo &LI,
if (!SeenOr.insert(Op).second)
continue;
OrWorklist.push_back(Op);
- Info.addFact(CmpInst::ICMP_SGE, Op,
- ConstantInt::getNullValue(Op->getType()), CB.NumIn,
- CB.NumOut, DFSInStack);
+ Info.addFact(Pred, Op, B, CB.NumIn, CB.NumOut, DFSInStack);
}
}
}
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