[llvm] [IR] Implementation and lowering of bitinsert and bitextract (PR #200605)

[Alexis Engelke via llvm-commits]

================
@@ -3557,6 +3557,67 @@ bool IRTranslator::translateShuffleVector(const User &U,
   return true;
 }
 
+bool IRTranslator::translateBitInsert(const User &U,
+                                      MachineIRBuilder &MIRBuilder) {
+  Register Res = getOrCreateVReg(U);
+  Register Base = getOrCreateVReg(*U.getOperand(0));
+  Register Val = getOrCreateVReg(*U.getOperand(1));
+  Register Offset = getOrCreateVReg(*U.getOperand(2));
+  MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+  LLT BaseTy = MRI.getType(Base);
+  LLT ValTy = MRI.getType(Val);
+
+  // Convert Offset to BaseTy.
+  Register LegalOffset = MIRBuilder.buildZExtOrTrunc(BaseTy, Offset).getReg(0);
+
+  Register RotatedBase =
+      MIRBuilder.buildRotateRight(BaseTy, Base, LegalOffset).getReg(0);
+
+  // Truncate or extend Val to BaseTy so only the inserted bit range remains.
+  Register ExtVal = MIRBuilder.buildZExtOrTrunc(BaseTy, Val).getReg(0);
+
+  // Clear the low ValBitWidth bits of the rotated base and insert Val there.
+  unsigned BaseBitWidth = BaseTy.getSizeInBits();
+  unsigned ValBitWidth = ValTy.getSizeInBits();
+  APInt ClearMask =
+      APInt::getHighBitsSet(BaseBitWidth, BaseBitWidth - ValBitWidth);
+  Register MaskConst = MIRBuilder.buildConstant(BaseTy, ClearMask).getReg(0);
+  Register ClearedBase =
+      MIRBuilder.buildAnd(BaseTy, RotatedBase, MaskConst).getReg(0);
+  Register Inserted = MIRBuilder.buildOr(BaseTy, ClearedBase, ExtVal).getReg(0);
+
+  // Restore bit positions by rotating back by the same amount.
+  MIRBuilder.buildRotateLeft(Res, Inserted, LegalOffset);
----------------
aengelke wrote:

Shift to match SelectionDAG.

https://github.com/llvm/llvm-project/pull/200605