[llvm] adc0f68 - AMDGPU: Convert tests to use subarch from triples in the file (#209869)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 02:16:18 PDT 2026
Author: Matt Arsenault
Date: 2026-07-16T11:16:13+02:00
New Revision: adc0f685fe94e66e68698ac87a8595e878477a61
URL: https://github.com/llvm/llvm-project/commit/adc0f685fe94e66e68698ac87a8595e878477a61
DIFF: https://github.com/llvm/llvm-project/commit/adc0f685fe94e66e68698ac87a8595e878477a61.diff
LOG: AMDGPU: Convert tests to use subarch from triples in the file (#209869)
This set was using target triple in the source rather than command
line arguments.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
llvm/test/CodeGen/AMDGPU/addrspacecast.ll
llvm/test/CodeGen/AMDGPU/amdgpu-llvm-debuginfo-analyzer.ll
llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll
llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll
llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
llvm/test/CodeGen/AMDGPU/issue176578.ll
llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
llvm/test/CodeGen/AMDGPU/pr155452.ll
llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
llvm/test/CodeGen/AMDGPU/vgpr-count-compute.ll
llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll
llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll
llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
index e207d95287783..cd5aad344dee4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
@@ -1,8 +1,5 @@
-; RUN: opt -passes=amdgpu-attributor -mcpu=gfx900 < %s | llc -mcpu=gfx900 | FileCheck -check-prefixes=GCN,RW-FLAT %s
-; RUN: opt -passes=amdgpu-attributor -mcpu=gfx900 -mattr=+architected-flat-scratch < %s | llc | FileCheck -check-prefixes=GCN,RO-FLAT %s
-; RUN: opt -passes=amdgpu-attributor -mcpu=gfx942 < %s | llc | FileCheck -check-prefixes=GCN,RO-FLAT %s
-
-target triple = "amdgcn-amd-amdhsa"
+; RUN: opt -mtriple=amdgpu9.00-amd-amdhsa -passes=amdgpu-attributor < %s | llc | FileCheck -check-prefixes=GCN,RW-FLAT %s
+; RUN: opt -mtriple=amdgpu9.42-amd-amdhsa -passes=amdgpu-attributor < %s | llc | FileCheck -check-prefixes=GCN,RO-FLAT %s
; Make sure flat_scratch_init is set
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
index 4652d0ae60fd0..18ed68396fa4f 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.ll
@@ -1,7 +1,5 @@
-; RUN: opt -passes=amdgpu-attributor -mcpu=kaveri -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | llc | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
-; RUN: opt -passes=amdgpu-attributor -mcpu=gfx900 -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | llc | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
-
-target triple = "amdgcn-amd-amdhsa"
+; RUN: opt -passes=amdgpu-attributor -mtriple=amdgpu7.00-amd-amdhsa -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | llc | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
+; RUN: opt -passes=amdgpu-attributor -mtriple=amdgpu9.00-amd-amdhsa -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | llc | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-llvm-debuginfo-analyzer.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-llvm-debuginfo-analyzer.ll
index d6922bc09ff0a..09d17a4d42781 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-llvm-debuginfo-analyzer.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-llvm-debuginfo-analyzer.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc %s -o %t.o -mcpu=gfx1030 -filetype=obj -O0
+; RUN: llc %s -o %t.o -mtriple=amdgpu10.30-amd-amdpal -filetype=obj -O0
; RUN: llvm-debuginfo-analyzer %t.o --print=all --attribute=all | FileCheck %s
; This test compiles this module with AMDGPU backend under -O0,
@@ -14,7 +14,6 @@
; CHECK: {Code} 's_endpgm'
source_filename = "module"
-target triple = "amdgcn-amd-amdpal"
%dx.types.ResRet.f32 = type { float, float, float, float, i32 }
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
index 67f2eb113d880..cc63ad0256b6a 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
@@ -1,7 +1,6 @@
-; RUN: opt -passes=amdgpu-attributor -mcpu=kaveri < %s | llc -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
-; RUN: opt -passes=amdgpu-attributor -mcpu=gfx900 < %s | llc -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
+; RUN: opt -passes=amdgpu-attributor -mtriple=amdgpu7.00-amd-amdhsa < %s | llc -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
+; RUN: opt -passes=amdgpu-attributor -mtriple=amdgpu9.00-amd-amdhsa < %s | llc -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
-target triple = "amdgcn-amd-amdhsa"
; GCN-LABEL: {{^}}use_dispatch_ptr:
; GCN: s_load_dword s{{[0-9]+}}, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
index a7009c4d20e33..6396ea498853a 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=amdgpu-attributor -mcpu=kaveri < %s | llc -mcpu=gfx90a -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN,GFX7 %s
-; RUN: opt -passes=amdgpu-attributor -mcpu=gfx90a -mattr=-xnack < %s | llc -mcpu=gfx90a -mattr=-xnack -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN,GFX90A %s
-
-target triple = "amdgcn-amd-amdhsa"
+; RUN: opt -mtriple=amdgpu7.00-amd-amdhsa -passes=amdgpu-attributor < %s | llc -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN,GFX7 %s
+; RUN: opt -mtriple=amdgpu9.0a-amd-amdhsa -passes=amdgpu-attributor -mattr=-xnack < %s | llc -mattr=-xnack -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN,GFX90A %s
define void @use_workitem_id_x() #1 {
; GFX7-LABEL: use_workitem_id_x:
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
index 718140f82887e..d17327e66bade 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -mcpu=kaveri -passes=amdgpu-attributor < %s | llc -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN %s
+; RUN: opt -mtriple=amdgpu7.00-amd-amdhsa -passes=amdgpu-attributor < %s | llc -enable-ipra=0 | FileCheck -enable-var-scope -check-prefixes=GCN %s
-target triple = "amdgcn-amd-amdhsa"
define void @use_workitem_id_x() #1 {
; GCN-LABEL: use_workitem_id_x:
diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll b/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
index 0ea51b2b3e212..dbc48ef0119b9 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-independence-adjustSchedDependency.ll
@@ -1,12 +1,11 @@
; RUN: opt %s -strip-debug -o %t.no_debug.ll -S
-; RUN: llc -mcpu=gfx1250 < %s -filetype=obj -o %t.with_debug.o
-; RUN: llc -mcpu=gfx1250 < %t.no_debug.ll -filetype=obj -o %t.no_debug.o
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa < %s -filetype=obj -o %t.with_debug.o
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa < %t.no_debug.ll -filetype=obj -o %t.no_debug.o
; RUN: llvm-strip %t.with_debug.o %t.no_debug.o
; RUN: cmp %t.with_debug.o %t.no_debug.o
; Ensure that compiling with and without debug generates identical code.
; Test that adjustSchedDependency does not count debug instructions in bundles.
-target triple = "amdgcn-amd-amdhsa"
define amdgpu_kernel void @_test_adjustSchedDependency(ptr addrspace(1) %AA.coerce, i64 %shiftA, i32 %lda, ptr addrspace(3) %stPtr) !dbg !4 {
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll b/llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll
index 148cbfcb89dcf..c093de5719f0f 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-independence-revertScheduling.ll
@@ -1,13 +1,12 @@
; RUN: opt %s -strip-debug -o %t.no_debug.ll -S
-; RUN: llc -O3 -mcpu=gfx1250 < %s -filetype=obj -o %t.with_debug.o
-; RUN: llc -O3 -mcpu=gfx1250 < %t.no_debug.ll -filetype=obj -o %t.no_debug.o
+; RUN: llc -O3 -mtriple=amdgpu12.50-amd-amdhsa < %s -filetype=obj -o %t.with_debug.o
+; RUN: llc -O3 -mtriple=amdgpu12.50-amd-amdhsa < %t.no_debug.ll -filetype=obj -o %t.no_debug.o
; RUN: llvm-strip %t.with_debug.o %t.no_debug.o
; RUN: cmp %t.with_debug.o %t.no_debug.o
; Ensure that compiling with and without debug generates identical code.
; Test that revertScheduling only updates LiveIntervals if non-debug
; instructions are reordered.
-target triple = "amdgcn-amd-amdhsa"
declare void @llvm.amdgcn.s.barrier() #0
diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll b/llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll
index 4e8dff12589df..6144d6f353770 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll
@@ -3,12 +3,11 @@
; instructions are reordered.
; RUN: opt %s -strip-debug -o %t.no_debug.ll -S
-; RUN: llc -O2 -mcpu=gfx1250 < %s -misched=gcn-iterative-ilp -filetype=obj -o %t.with_debug.o
-; RUN: llc -O2 -mcpu=gfx1250 < %t.no_debug.ll -misched=gcn-iterative-ilp -filetype=obj -o %t.no_debug.o
+; RUN: llc -O2 -mtriple=amdgpu12.50-amd-amdhsa < %s -misched=gcn-iterative-ilp -filetype=obj -o %t.with_debug.o
+; RUN: llc -O2 -mtriple=amdgpu12.50-amd-amdhsa < %t.no_debug.ll -misched=gcn-iterative-ilp -filetype=obj -o %t.no_debug.o
; RUN: llvm-strip %t.with_debug.o %t.no_debug.o
; RUN: cmp %t.with_debug.o %t.no_debug.o
-target triple = "amdgcn-amd-amdhsa"
declare void @llvm.amdgcn.s.barrier() #0
diff --git a/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll b/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
index cbda0621a3181..de1a1a36baa5d 100644
--- a/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
@@ -1,26 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -mattr=+fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=preserve-sign -mattr=-fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=ieee -mattr=+fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-FASTFMA,SI-DENORM-FASTFMA-STRICT %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=ieee -mattr=-fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-SLOWFMA %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00-- -denormal-fp-math-f32=preserve-sign -mattr=+fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.01-- -denormal-fp-math-f32=preserve-sign -mattr=-fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00-- -denormal-fp-math-f32=ieee -mattr=+fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-FASTFMA,SI-DENORM-FASTFMA-STRICT %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.01-- -denormal-fp-math-f32=ieee -mattr=-fast-fmaf -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-SLOWFMA %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -mattr=+fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=preserve-sign -mattr=-fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tahiti -denormal-fp-math-f32=ieee -mattr=+fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-FASTFMA,SI-DENORM-FASTFMA-CONTRACT %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=verde -denormal-fp-math-f32=ieee -mattr=-fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-SLOWFMA %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00-- -denormal-fp-math-f32=preserve-sign -mattr=+fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.01-- -denormal-fp-math-f32=preserve-sign -mattr=-fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-FLUSH %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00-- -denormal-fp-math-f32=ieee -mattr=+fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-FASTFMA,SI-DENORM-FASTFMA-CONTRACT %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.01-- -denormal-fp-math-f32=ieee -mattr=-fast-fmaf -fp-contract=fast < %s | FileCheck -enable-var-scope -check-prefixes=SI-DENORM-SLOWFMA %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-FLUSH,GFX9-FLUSH-MAD %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -denormal-fp-math-f32=ieee -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-DENORM,GFX9-DENORM-FASTFMA-MAD %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.00-- -denormal-fp-math-f32=preserve-sign -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-FLUSH,GFX9-FLUSH-MAD %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.00-- -denormal-fp-math-f32=ieee -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-DENORM,GFX9-DENORM-FASTFMA-MAD %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx906 -denormal-fp-math-f32=preserve-sign -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-FLUSH,GFX9-FLUSH-FMAC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx906 -denormal-fp-math-f32=ieee -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-DENORM,GFX9-DENORM-FASTFMA-FMAC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.06-- -denormal-fp-math-f32=preserve-sign -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-FLUSH,GFX9-FLUSH-FMAC %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.06-- -denormal-fp-math-f32=ieee -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-DENORM,GFX9-DENORM-FASTFMA-FMAC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx1030 -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX10-FLUSH %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx1030 -denormal-fp-math-f32=ieee -mattr=+mad-mac-f32-insts -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX10-DENORM %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu10.30-- -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX10-FLUSH %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu10.30-- -denormal-fp-math-f32=ieee -mattr=+mad-mac-f32-insts -fp-contract=on < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX10-DENORM %s
; Test all permutations of: fp32 denormals, fast fp contract, fp contract enabled for fmuladd, fmaf fast/slow.
-target triple = "amdgcn--"
declare i32 @llvm.amdgcn.workitem.id.x() #1
declare float @llvm.fmuladd.f32(float, float, float) #1
diff --git a/llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll b/llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
index 7c8d89ef03b1b..f5ce54208250b 100644
--- a/llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
+++ b/llvm/test/CodeGen/AMDGPU/implicitarg-attributes.ll
@@ -1,6 +1,5 @@
-; RUN: opt -passes=amdgpu-attributor < %s | llc | FileCheck %s
+; RUN: opt -mtriple=amdgpu9.00-amd-amdhsa -passes=amdgpu-attributor < %s | llc | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
; The call to intrinsic implicitarg_ptr reaches a load through a phi. The
; offsets of the phi cannot be determined, and hence the attirbutor assumes that
diff --git a/llvm/test/CodeGen/AMDGPU/issue176578.ll b/llvm/test/CodeGen/AMDGPU/issue176578.ll
index 255fea7098191..a6a4579fb6a43 100644
--- a/llvm/test/CodeGen/AMDGPU/issue176578.ll
+++ b/llvm/test/CodeGen/AMDGPU/issue176578.ll
@@ -1,10 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mcpu=gfx900 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s
; Check for assert when trying to optimize s_and_b64 + s_cbranch_vccz
; pattern.
-target triple = "amdgcn-amd-amdhsa"
declare hidden void @func(<4 x i8>, <2 x i8>)
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
index 252c49eaa87b2..ecee3ae3ea45b 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
@@ -1,5 +1,4 @@
-; RUN: llc -mcpu=gfx906 -o - < %s | FileCheck --check-prefix=CHECK %s
-target triple = "amdgcn-amd-amdhsa"
+; RUN: llc -mtriple=amdgpu9.06-amd-amdhsa -o - < %s | FileCheck --check-prefix=CHECK %s
; Check the group segment has size 4, not zero.
; CHECK: .amdhsa_kernel __device_start
diff --git a/llvm/test/CodeGen/AMDGPU/pr155452.ll b/llvm/test/CodeGen/AMDGPU/pr155452.ll
index b51b6ee07aea5..b70e6c5b0e9f7 100644
--- a/llvm/test/CodeGen/AMDGPU/pr155452.ll
+++ b/llvm/test/CodeGen/AMDGPU/pr155452.ll
@@ -1,67 +1,63 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s | FileCheck %s
-
-target triple = "amdgcn-amd-amdhsa"
+; RUN: llc -mtriple=amdgpu6.00-amd-amdhsa < %s | FileCheck %s
define amdgpu_kernel void @my_kernel(i64 %foo, i32 %bar) {
; CHECK-LABEL: my_kernel:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_mov_b32 flat_scratch_lo, s13
-; CHECK-NEXT: s_add_i32 s12, s12, s17
-; CHECK-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
-; CHECK-NEXT: s_load_dword s0, s[8:9], 0x2
-; CHECK-NEXT: s_load_dwordx2 s[2:3], s[8:9], 0x0
-; CHECK-NEXT: s_mov_b64 s[4:5], 1
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_load_dword s7, s[8:9], 0x2
+; CHECK-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
+; CHECK-NEXT: s_mov_b32 s3, 0x100f000
+; CHECK-NEXT: s_mov_b32 s2, -1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: s_ashr_i32 s6, s0, 31
-; CHECK-NEXT: s_abs_i32 s7, s0
-; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s7
-; CHECK-NEXT: s_sub_i32 s0, 0, s7
-; CHECK-NEXT: v_rcp_f32_e32 v2, v2
-; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT: v_mul_lo_u32 v3, s0, v2
-; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3
-; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT: s_and_b64 s[0:1], exec, -1
+; CHECK-NEXT: s_abs_i32 s6, s7
+; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s6
+; CHECK-NEXT: s_sub_i32 s0, 0, s6
+; CHECK-NEXT: s_ashr_i32 s7, s7, 31
+; CHECK-NEXT: v_rcp_f32_e32 v0, v0
+; CHECK-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
+; CHECK-NEXT: v_mul_lo_u32 v1, s0, v0
+; CHECK-NEXT: s_mov_b64 s[0:1], 1
+; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1
+; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT: s_and_b64 vcc, exec, -1
; CHECK-NEXT: .LBB0_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: v_mov_b32_e32 v3, s4
-; CHECK-NEXT: v_mad_u64_u32 v[3:4], s[8:9], s2, v3, 1
-; CHECK-NEXT: s_mul_i32 s4, s3, s4
-; CHECK-NEXT: s_mul_i32 s5, s2, s5
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, s4, v4
-; CHECK-NEXT: v_readfirstlane_b32 s4, v3
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, s5, v4
-; CHECK-NEXT: s_ashr_i32 s5, s4, 31
-; CHECK-NEXT: s_abs_i32 s8, s4
-; CHECK-NEXT: s_xor_b32 s5, s5, s6
-; CHECK-NEXT: v_mul_hi_u32 v3, s8, v2
-; CHECK-NEXT: v_readfirstlane_b32 s9, v3
-; CHECK-NEXT: v_add_i32_e32 v5, vcc, 1, v3
-; CHECK-NEXT: s_mul_i32 s9, s9, s7
-; CHECK-NEXT: s_sub_i32 s8, s8, s9
-; CHECK-NEXT: s_sub_i32 s9, s8, s7
-; CHECK-NEXT: s_cmp_ge_u32 s8, s7
-; CHECK-NEXT: s_cselect_b64 vcc, -1, 0
-; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; CHECK-NEXT: s_cselect_b32 s8, s9, s8
-; CHECK-NEXT: v_add_i32_e32 v5, vcc, 1, v3
-; CHECK-NEXT: s_cmp_ge_u32 s8, s7
-; CHECK-NEXT: s_cselect_b64 vcc, -1, 0
-; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; CHECK-NEXT: v_xor_b32_e32 v3, s5, v3
-; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s5, v3
-; CHECK-NEXT: v_ashrrev_i32_e32 v5, 31, v3
-; CHECK-NEXT: v_or_b32_e32 v3, s4, v3
-; CHECK-NEXT: v_or_b32_e32 v4, v4, v5
-; CHECK-NEXT: flat_load_dwordx2 v[3:4], v[3:4]
+; CHECK-NEXT: s_waitcnt expcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v1, s0
+; CHECK-NEXT: v_mul_hi_u32 v1, s4, v1
+; CHECK-NEXT: s_mul_i32 s1, s4, s1
+; CHECK-NEXT: s_mul_i32 s8, s5, s0
+; CHECK-NEXT: s_mul_i32 s0, s4, s0
+; CHECK-NEXT: v_readfirstlane_b32 s9, v1
+; CHECK-NEXT: s_add_i32 s1, s9, s1
+; CHECK-NEXT: s_add_i32 s1, s1, s8
+; CHECK-NEXT: s_add_u32 s0, s0, 1
+; CHECK-NEXT: s_addc_u32 s1, s1, 0
+; CHECK-NEXT: s_abs_i32 s9, s0
+; CHECK-NEXT: v_mul_hi_u32 v1, s9, v0
+; CHECK-NEXT: s_ashr_i32 s8, s0, 31
+; CHECK-NEXT: s_xor_b32 s8, s8, s7
+; CHECK-NEXT: v_readfirstlane_b32 s10, v1
+; CHECK-NEXT: s_mul_i32 s11, s10, s6
+; CHECK-NEXT: s_sub_i32 s9, s9, s11
+; CHECK-NEXT: s_add_i32 s12, s10, 1
+; CHECK-NEXT: s_sub_i32 s11, s9, s6
+; CHECK-NEXT: s_cmp_ge_u32 s9, s6
+; CHECK-NEXT: s_cselect_b32 s10, s12, s10
+; CHECK-NEXT: s_cselect_b32 s9, s11, s9
+; CHECK-NEXT: s_add_i32 s11, s10, 1
+; CHECK-NEXT: s_cmp_ge_u32 s9, s6
+; CHECK-NEXT: s_cselect_b32 s9, s11, s10
+; CHECK-NEXT: s_xor_b32 s9, s9, s8
+; CHECK-NEXT: s_sub_i32 s8, s9, s8
+; CHECK-NEXT: s_ashr_i32 s9, s8, 31
+; CHECK-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
+; CHECK-NEXT: buffer_load_dwordx2 v[1:2], off, s[0:3], 0
+; CHECK-NEXT: s_mov_b64 s[0:1], 0
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[3:4]
-; CHECK-NEXT: s_mov_b64 s[4:5], 0
-; CHECK-NEXT: s_mov_b64 vcc, s[0:1]
+; CHECK-NEXT: buffer_store_dwordx2 v[1:2], off, s[0:3], 0
+; CHECK-NEXT: s_mov_b64 vcc, vcc
; CHECK-NEXT: s_cbranch_vccnz .LBB0_1
; CHECK-NEXT: ; %bb.2: ; %DummyReturnBlock
; CHECK-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll b/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
index fe28d7beea8ba..30ef11ffea70f 100644
--- a/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
@@ -1,7 +1,6 @@
-; RUN: llc -filetype=null %s
+; RUN: llc -mtriple=amdgpu6.00-- -filetype=null %s
; Check that renameDisconnectedComponents() does not create vregs without a
; definition on every path (there should at least be IMPLICIT_DEF instructions).
-target triple = "amdgcn--"
define amdgpu_kernel void @func(i1 %c0, i1 %c1, i1 %c2) {
B0:
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
index df7acbbc03ed4..2260854945e8b 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mcpu=gfx942 -amdgpu-mfma-vgpr-form < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -amdgpu-mfma-vgpr-form < %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
define amdgpu_kernel void @test_rewrite_mfma_copy_to_agpr_phi(ptr addrspace(1) %arg0, ptr addrspace(1) %arg1, i1 %cond) #0 {
; CHECK-LABEL: test_rewrite_mfma_copy_to_agpr_phi:
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
index 7d00b12e7334a..c93de664b3bdf 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mcpu=gfx90a -amdgpu-mfma-vgpr-form < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -amdgpu-mfma-vgpr-form < %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
define void @test_rewrite_mfma_i32_32x32x8i8(i32 %arg0, i32 %arg1, ptr addrspace(1) %ptr) #0 {
; CHECK-LABEL: test_rewrite_mfma_i32_32x32x8i8:
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
index b2465b02f2eee..b163b57883481 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mcpu=gfx950 -amdgpu-mfma-vgpr-form < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -amdgpu-mfma-vgpr-form < %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
define void @test_rewrite_mfma_f32_16x16x32_f16(<8 x half> %arg0, <8 x half> %arg1, ptr addrspace(1) %ptr) #0 {
; CHECK-LABEL: test_rewrite_mfma_f32_16x16x32_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
index 1144a3d310d02..8e4832f7f9e6d 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -verify-machineinstrs -mcpu=gfx942 -amdgpu-mfma-vgpr-form < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=amdgpu9.42-amd-amdhsa -amdgpu-mfma-vgpr-form < %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
define amdgpu_kernel void @respect_optnone(double %arg0, double %arg1, ptr addrspace(1) %ptr) #4 {
; CHECK-LABEL: respect_optnone:
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-count-compute.ll b/llvm/test/CodeGen/AMDGPU/vgpr-count-compute.ll
index 71d4e6b277320..c789726dc1413 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-count-compute.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-count-compute.ll
@@ -1,6 +1,5 @@
-; RUN: llc -mcpu=gfx1200 < %s | FileCheck %s --check-prefixes=CHECK,PACKED
-; RUN: llc -mcpu=gfx1030 < %s | FileCheck %s --check-prefixes=CHECK,NOTPACKED
-target triple = "amdgcn-amd-amdhsa"
+; RUN: llc -mtriple=amdgpu12.00-amd-amdhsa < %s | FileCheck %s --check-prefixes=CHECK,PACKED
+; RUN: llc -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck %s --check-prefixes=CHECK,NOTPACKED
@global = addrspace(1) global i32 poison, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll b/llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll
index a9f4bda12c557..78cf92e2c8dfe 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-count-graphics-chain.ll
@@ -1,5 +1,4 @@
-; RUN: llc -mcpu=gfx1200 < %s | FileCheck %s
-target triple = "amdgcn--amdpal"
+; RUN: llc -mtriple=amdgpu12.00--amdpal < %s | FileCheck %s
@global = addrspace(1) global i32 poison, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll b/llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll
index ea19763d61f41..94ec9b9f0aa11 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-count-graphics.ll
@@ -1,5 +1,4 @@
-; RUN: llc -mcpu=gfx1200 < %s | FileCheck %s
-target triple = "amdgcn--amdpal"
+; RUN: llc -mtriple=amdgpu12.00--amdpal < %s | FileCheck %s
@global = addrspace(1) global i32 poison, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll b/llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
index 7a8d66ba84b75..59dbaaa333b7d 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mcpu=gfx1030 < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
; Unknown functions are conservatively passed all implicit parameters
declare fastcc void @unknown_call()
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