[llvm] dab4c91 - [TableGen] Optimize register bank and info emission. (#208297)

[via llvm-commits]

Author: roman1741941
Date: 2026-07-16T08:11:40Z
New Revision: dab4c918c2453cc5650563571c35c6949bf5c611

URL: https://github.com/llvm/llvm-project/commit/dab4c918c2453cc5650563571c35c6949bf5c611
DIFF: https://github.com/llvm/llvm-project/commit/dab4c918c2453cc5650563571c35c6949bf5c611.diff

LOG: [TableGen] Optimize register bank and info emission. (#208297)

Don't go via a BitVector just to a read a single value out of it.

Added: 
    

Modified: 
    llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    llvm/utils/TableGen/Common/CodeGenRegisters.h
    llvm/utils/TableGen/RegisterBankEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index cbbce39e267d9..113edb109551c 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -1024,18 +1024,12 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
          "Biggest class wasn't first");
 
   // Find all the subreg classes and order them by size too.
-  std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses;
+  std::vector<CodeGenRegisterClass *> SuperRegClasses;
   for (auto &RC : RegClasses) {
-    BitVector SuperRegClassesBV(RegClasses.size());
-    RC.getSuperRegClasses(SubIdx, SuperRegClassesBV);
-    if (SuperRegClassesBV.any())
-      SuperRegClasses.emplace_back(&RC, SuperRegClassesBV);
+    if (RC.hasAnySuperRegClasses(SubIdx))
+      SuperRegClasses.push_back(&RC);
   }
-  llvm::stable_sort(SuperRegClasses,
-                    [&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
-                        const std::pair<CodeGenRegisterClass *, BitVector> &B) {
-                      return WeakSizeOrder(A.first, B.first);
-                    });
+  llvm::stable_sort(SuperRegClasses, WeakSizeOrder);
 
   // Find the biggest subclass and subreg class such that R:subidx is in the
   // subreg class for all R in subclass.
@@ -1049,8 +1043,8 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
   CodeGenRegisterClass *ChosenSuperRegClass = nullptr;
   CodeGenRegisterClass *SubRegRC = nullptr;
   for (CodeGenRegisterClass *SuperRegRC : SuperRegRCs) {
-    for (const auto &[SuperRegClass, SuperRegClassBV] : SuperRegClasses) {
-      if (SuperRegClassBV[SuperRegRC->EnumValue]) {
+    for (CodeGenRegisterClass *SuperRegClass : SuperRegClasses) {
+      if (SuperRegClass->hasSuperRegClass(SubIdx, SuperRegRC)) {
         SubRegRC = SuperRegClass;
         ChosenSuperRegClass = SuperRegRC;
 
@@ -1077,6 +1071,18 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
   return std::nullopt;
 }
 
+bool CodeGenRegisterClass::hasAnySuperRegClasses(
+    const CodeGenSubRegIndex *SubIdx) const {
+  return SuperRegClasses.contains(SubIdx);
+}
+
+bool CodeGenRegisterClass::hasSuperRegClass(
+    const CodeGenSubRegIndex *SubIdx, const CodeGenRegisterClass *RC) const {
+  auto FindI = SuperRegClasses.find(SubIdx);
+
+  return FindI != SuperRegClasses.end() && FindI->second.contains(RC);
+}
+
 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
                                               BitVector &Out) const {
   auto FindI = SuperRegClasses.find(SubIdx);

diff  --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 077294783f8ae..e733da1971eec 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -447,6 +447,15 @@ class CodeGenRegisterClass {
     SubClassWithSubReg[SubIdx] = SubRC;
   }
 
+  /// Checks if there are any super-register classes for this SubIdx of this
+  /// class.
+  bool hasAnySuperRegClasses(const CodeGenSubRegIndex *SubIdx) const;
+
+  /// Checks if there is a super-register class for this SubIdx of this
+  /// class containing RC register class.
+  bool hasSuperRegClass(const CodeGenSubRegIndex *SubIdx,
+                        const CodeGenRegisterClass *RC) const;
+
   // getSuperRegClasses - Returns a bit vector of all register classes
   // containing only SubIdx super-registers of this class.
   void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,

diff  --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index c2cb06fe456c7..c53aca4444057 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -206,9 +206,7 @@ static void visitRegisterBankClasses(
     // PossibleSubclass for all registers Reg from RC using any
     // subregister-index SubReg
     for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
-      BitVector BV(RegisterClassHierarchy.getRegClasses().size());
-      PossibleSubclass.getSuperRegClasses(&SubIdx, BV);
-      if (BV.test(RC->EnumValue)) {
+      if (PossibleSubclass.hasSuperRegClass(&SubIdx, RC)) {
         std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +
                                 " class-with-subregs: " + RC->getName())
                                    .str();