[llvm] [X86] Interleave independent reductions to share cross-lane extracts (PR #209963)
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Wed Jul 15 21:54:10 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Pranav Gorantla (pranav-159)
<details>
<summary>Changes</summary>
A horizontal reduction collapses all lanes of a vector to a scalar. Reaching a 128-bit lane requires cross-lane extracts - vextracti64x4 (512->256) and vextracti128 (256->128) - which are the costly part: a cross-lane move is higher latency than the in-lane folds and competes for the limited vector-shuffle throughput, the bottleneck when several reductions run together. N independent reductions pay that extract chain N times.
The transform interleaves the reductions' inputs into a single register with unpck shuffles (whose steps also apply the reduction op), then runs one shared reduction over that register, leaving one result per lane. The expensive cross-lane extracts are done once for the whole group instead of once per reduction, trading N-1 extract chains for cheaper in-lane shuffles.
Each <16 x i32> add reduction, on its own, is:
vextracti64x4 ; 512 -> 256, cross-lane
vpaddd
vextracti128 ; 256 -> 128, cross-lane
vpaddd
vpshufd ; in-lane tail
vpaddd
vpshufd
vpaddd
so two of them pay both extracts twice. Interleaved:
vpunpckldq A, B
vpunpckhdq A, B
vpaddd
vextracti64x4 ; shared by A and B
vpaddd
vextracti128 ; shared by A and B
vpaddd
vpshufd ; in-lane reduction step, shared
vpaddd
vmovd ; A = lane 0
vpextrd ; B = lane 1
Gated on the prefer-unpck-over-cross-lane-extract subtarget feature (znver4/znver5); inert elsewhere. Runs after combineArithReduction so op/type-specific lowerings (e.g. vXi8 add -> PSADBW) win first. Only fires for integer reductions whose input is register-sourced (CopyFromReg leaves) and independent of the other fused reductions, >= 256 bits, with >= 2 same-shape siblings.
Assisted-by: Claude Opus 4.7 <noreply@<!-- -->anthropic.com>
---
Patch is 45.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209963.diff
3 Files Affected:
- (modified) llvm/lib/Target/X86/X86.td (+9-1)
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+186)
- (added) llvm/test/CodeGen/X86/vector-reduce-interleave.ll (+775)
``````````diff
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index b724a12d2f698..f55bdfa9abba1 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -842,6 +842,13 @@ def TuningFastHorizontalOps
"normal vector instructions with shuffles",
[], InlineIgnore>;
+def TuningPreferUnpckOverCrossLaneExtract
+ : SubtargetFeature<"prefer-unpck-over-cross-lane-extract",
+ "PreferUnpckOverCrossLaneExtract", "true",
+ "Prefer unpck shuffles over cross-lane extracts, e.g. to "
+ "share extracts across independent vector reductions",
+ [], InlineIgnore>;
+
def TuningFastScalarShiftMasks
: SubtargetFeature<
"fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
@@ -1723,7 +1730,8 @@ def ProcessorFeatures {
list<SubtargetFeature> ZN4AdditionalTuning = [TuningFastDPWSSD,
TuningCOMPRESSFalseDeps,
- TuningEXPANDFalseDeps];
+ TuningEXPANDFalseDeps,
+ TuningPreferUnpckOverCrossLaneExtract];
list<SubtargetFeature> ZN4Tuning =
!listconcat(ZN3Tuning, ZN4AdditionalTuning);
list<SubtargetFeature> ZN4AdditionalFeatures = [FeatureAVX512,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index bb4b13e4feca4..e085b577e3da1 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -47929,6 +47929,186 @@ static SDValue combineArithReduction(SDNode *ExtElt, SelectionDAG &DAG,
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Rdx, Index);
}
+//===----------------------------------------------------------------------===//
+// X86 multiple-reduction interleaving.
+//
+// Fuse independent same-(opcode, element-type) reductions to share their
+// cross-lane extracts (vextracti64x4 512->256, vextracti128 256->128) -- the
+// dominant cost of a reduction. Without this each of the N reductions extracts
+// on its own; interleaving with unpck lets a single shared descent reduce all N,
+// cutting the total instruction count (one set of extracts and folds, not N).
+// Two <8 x i32> adds:
+//
+// A ; [a0 a1 a2 a3 | a4 a5 a6 a7]
+// hi = vextracti128 A ; [a4 a5 a6 a7] cross-lane, A only
+// a = add A.lo, hi ; [a0+a4 a1+a5 a2+a6 a3+a7]
+// ... in-lane fold ; a[0] = sum(A); B repeats -> a second vextracti128
+//
+// unpck mixes sibling reductions into one register; one fold reduces A and B:
+//
+// lo = unpcklo A, B ; [a0 b0 a1 b1 | a4 b4 a5 b5]
+// hi = unpckhi A, B ; [a2 b2 a3 b3 | a6 b6 a7 b7]
+// p = add lo, hi ; [a0+a2 b0+b2 a1+a3 b1+b3 |
+// a4+a6 b4+b6 a5+a7 b5+b7] A even, B odd
+// hi = vextracti128 p ; [a4+a6 b4+b6 a5+a7 b5+b7] ONE extract, shared
+// p = add p.lo, hi ; [a0+a2+a4+a6 b0+b2+b4+b6
+// a1+a3+a5+a7 b1+b3+b5+b7] still: a even, b odd
+// ... in-lane fold ; p = [sum(A) sum(B)] in lanes 0, 1
+//
+// Returns the triggering extract's result and replaces the other reductions'
+// extracts in the DAG.
+//===----------------------------------------------------------------------===//
+// Balanced pow2 interleave puts reduction r's result in lane reverseBits(r)
+// (over log2(N) bits), so member r is extracted from there:
+// N=2: r = 0,1 -> lane 0,1
+// N=4: r = 0,1,2,3 -> lane 0,2,1,3
+static void emitInterleavedReductions(SelectionDAG &DAG, const SDLoc &DL,
+ ArrayRef<std::pair<SDValue, SDNode *>> Group,
+ unsigned Op,
+ SmallVectorImpl<std::pair<SDNode *, SDValue>> &Repl) {
+ unsigned N = Group.size();
+ assert(N >= 2 && isPowerOf2_32(N) &&
+ "group must be a power of 2 >= 2 (LogN >= 1 for the lane shift)");
+ unsigned LogN = Log2_32(N);
+ SmallVector<SDValue, 16> V;
+ for (const auto &C : Group)
+ V.push_back(C.first);
+ // Pairwise tree: each level interleaves adjacent pairs in place, halving V
+ // until one vector packs all inputs.
+ while (V.size() > 1) {
+ unsigned NumOps = V.size();
+ for (unsigned i = 0; i != NumOps; i += 2) {
+ SDValue L = V[i], R = V[i + 1];
+ EVT VT = L.getValueType();
+ // op(unpcklo(L,R), unpckhi(L,R)): riffle L and R together and fold, so one
+ // vector carries both (L in even lanes, R in odd).
+ V[i / 2] = DAG.getNode(Op, DL, VT, getUnpackl(DAG, DL, VT, L, R),
+ getUnpackh(DAG, DL, VT, L, R));
+ }
+ V.resize(NumOps / 2);
+ }
+ // Shared descent: fold the packed vector until each reduction owns one lane,
+ // narrowing with SplitVector while the halved op stays legal (minimal widths).
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ SDValue Packed = V[0];
+ while (Packed.getValueType().getVectorNumElements() > N) {
+ EVT VT = Packed.getValueType();
+ EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
+ if (!TLI.isOperationLegalOrCustom(Op, HalfVT))
+ break;
+ auto [Lo, Hi] = DAG.SplitVector(Packed, DL);
+ Packed = DAG.getNode(Op, DL, HalfVT, Lo, Hi);
+ }
+ // The narrowing above stops at the smallest legal vector width (128-bit on
+ // x86); finish the tail in-register there.
+ EVT PackedVT = Packed.getValueType();
+ unsigned NumElts = PackedVT.getVectorNumElements();
+ SDValue Undef = DAG.getUNDEF(PackedVT);
+ for (unsigned W = NumElts; W > N; W >>= 1) {
+ SDValue Hi = DAG.getVectorShuffle(
+ PackedVT, DL, Packed, Undef,
+ createSequentialMask(W / 2, W / 2, NumElts - W / 2));
+ Packed = DAG.getNode(Op, DL, PackedVT, Packed, Hi);
+ }
+ // Extract each reduction's result from its lane (reverseBits(r)) and pair it
+ // with the original extract node to replace.
+ for (unsigned r = 0; r < N; ++r) {
+ unsigned Lane = APInt(LogN, r).reverseBits().getZExtValue();
+ EVT ResVT = Group[r].second->getValueType(0);
+ SDValue Out = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Packed,
+ DAG.getVectorIdxConstant(Lane, DL));
+ Repl.emplace_back(Group[r].second, Out);
+ }
+}
+// Reduction opcodes we interleave.
+// TODO: extend to FP (fadd/fmul).
+static constexpr ISD::NodeType InterleavableReductionOps[] = {
+ ISD::ADD, ISD::MUL, ISD::AND, ISD::OR, ISD::XOR,
+ ISD::SMAX, ISD::SMIN, ISD::UMAX, ISD::UMIN};
+
+// True if V (a reduction's input) is independent of the reductions being fused:
+// its operand chain (<= Depth) bottoms out in CopyFromReg leaves and contains no
+// EXTRACT_VECTOR_ELT, so it cannot hold another fused reduction's result.
+static bool isIndependentReductionInput(SDValue V, unsigned Depth = 4) {
+ if (V.getOpcode() == ISD::CopyFromReg)
+ return true;
+ if (Depth == 0 || V.getNumOperands() == 0 ||
+ V.getOpcode() == ISD::EXTRACT_VECTOR_ELT)
+ return false;
+ for (SDValue O : V->op_values())
+ if (!isIndependentReductionInput(O, Depth - 1))
+ return false;
+ return true;
+}
+
+static SDValue combineMultipleReductions(SDNode *ExtN, SelectionDAG &DAG,
+ TargetLowering::DAGCombinerInfo &DCI,
+ const X86Subtarget &Subtarget) {
+ if (!Subtarget.preferUnpckOverCrossLaneExtract())
+ return SDValue();
+
+ // Only match reductions whose input is independent (see isIndependentReductionInput).
+ // Note: after fusing, each result depends on ALL fused inputs (the shared
+ // interleave consumes them together), not just its own -- a false dependency,
+ // so a late input delays every result and can lengthen the critical path. In
+ // practice we have not found real-world code that regresses because of it.
+ ISD::NodeType TrigBinOp;
+ SDValue TrigRoot =
+ DAG.matchBinOpReduction(ExtN, TrigBinOp, InterleavableReductionOps);
+ if (!TrigRoot || !TrigRoot.getValueType().isFixedLengthVector() ||
+ !isIndependentReductionInput(TrigRoot))
+ return SDValue();
+ EVT VT = TrigRoot.getValueType();
+ if (VT.getFixedSizeInBits() < 256) // 128-bit: no cross-lane extract to share
+ return SDValue();
+ unsigned EltBits = VT.getScalarSizeInBits();
+
+ // Gather sibling reductions with the same opcode, vector type, and an
+ // independent input. ExtN goes first so it always lands in the first chunk.
+ SmallVector<std::pair<SDValue, SDNode *>, 8> Work;
+ Work.push_back({TrigRoot, ExtN});
+ for (SDNode &N : DAG.allnodes()) {
+ if (&N == ExtN || N.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
+ continue;
+ ISD::NodeType BinOp;
+ SDValue Root = DAG.matchBinOpReduction(&N, BinOp, TrigBinOp);
+ if (Root && Root.getValueType() == VT && isIndependentReductionInput(Root))
+ Work.push_back({Root, &N});
+ }
+ if (Work.size() < 2)
+ return SDValue();
+
+ // Group size is capped at the number of elements in one 128-bit lane, which
+ // keeps the balanced interleave within a lane so result r lands in lane
+ // reverseBits(r) (see emitInterleavedReductions).
+ unsigned Cap = 128 / EltBits;
+
+ // Interleave the group in balanced pow2 chunks, each up to one 128-bit lane.
+ // TODO: add support for non-pow2 groups; a lone remainder (e.g. 3 -> {2, 1})
+ // is reduced on its own (packing it in could lengthen the critical path).
+ SmallVector<std::pair<SDNode *, SDValue>, 16> Repl;
+ while (Work.size() >= 2) {
+ unsigned Take = std::min<unsigned>(Cap, llvm::bit_floor<uint32_t>(Work.size()));
+ SDLoc DL(Work.front().second); // tag this chunk's nodes with its own location
+ emitInterleavedReductions(
+ DAG, DL, ArrayRef<std::pair<SDValue, SDNode *>>(Work).take_front(Take),
+ TrigBinOp, Repl);
+ Work.erase(Work.begin(), Work.begin() + Take);
+ }
+ if (Repl.empty())
+ return SDValue();
+
+ // Wire in the interleaved results; return the trigger's replacement.
+ SDValue TriggerNew;
+ for (auto &P : Repl) {
+ if (P.first == ExtN)
+ TriggerNew = P.second;
+ else
+ DCI.CombineTo(P.first, P.second);
+ }
+ return DCI.CombineTo(ExtN, TriggerNew);
+}
+
/// Detect vector gather/scatter index generation and convert it from being a
/// bunch of shuffles and extracts into a somewhat faster sequence.
/// For i686, the best sequence is apparently storing the value and loading
@@ -48048,6 +48228,12 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
if (SDValue V = combineArithReduction(N, DAG, Subtarget))
return V;
+ // Interleave independent sibling reductions to share cross-lane extracts.
+ // Runs after the op/type-specific reduction combines above (e.g. i8 add ->
+ // PSADBW) so those win; we only claim reductions they leave as extract chains.
+ if (SDValue V = combineMultipleReductions(N, DAG, DCI, Subtarget))
+ return V;
+
if (SDValue V = scalarizeExtEltFP(N, DAG, Subtarget, DCI))
return V;
diff --git a/llvm/test/CodeGen/X86/vector-reduce-interleave.ll b/llvm/test/CodeGen/X86/vector-reduce-interleave.ll
new file mode 100644
index 0000000000000..e30528619b42f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-reduce-interleave.ll
@@ -0,0 +1,775 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq,+prefer-unpck-over-cross-lane-extract | FileCheck %s --check-prefixes=CHECK,UNPCK
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=CHECK,BASE
+
+; UNPCK (feature on): independent same-(opcode, element type) reductions of
+; live-in vectors share one cross-lane extract chain (vpunpck interleave).
+; BASE (feature off): each reduction keeps its own cross-lane extract chain.
+
+declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
+declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
+declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
+declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8>)
+declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
+declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)
+declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)
+
+; i32/512, N=2.
+define i32 @add_i32_512_n2(<16 x i32> %a, <16 x i32> %b) {
+; UNPCK-LABEL: add_i32_512_n2:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm2 = zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[14],zmm0[14],zmm1[15],zmm0[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[12],zmm0[12],zmm1[13],zmm0[13]
+; UNPCK-NEXT: vpaddd %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i32_512_n2:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm2
+; BASE-NEXT: vpaddd %zmm2, %zmm0, %zmm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm2
+; BASE-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,1,1]
+; BASE-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm0
+; BASE-NEXT: vpaddd %zmm0, %zmm1, %zmm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: imull %ecx, %eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %b)
+ %r = mul i32 %ra, %rb
+ ret i32 %r
+}
+
+; i32/512, N=4.
+define i32 @add_i32_512_n4(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i32> %d) {
+; UNPCK-LABEL: add_i32_512_n4:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm4 = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm1 = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13]
+; UNPCK-NEXT: vpaddd %zmm4, %zmm1, %zmm1
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm2 = zmm3[2],zmm0[2],zmm3[3],zmm0[3],zmm3[6],zmm0[6],zmm3[7],zmm0[7],zmm3[10],zmm0[10],zmm3[11],zmm0[11],zmm3[14],zmm0[14],zmm3[15],zmm0[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm3[0],zmm0[0],zmm3[1],zmm0[1],zmm3[4],zmm0[4],zmm3[5],zmm0[5],zmm3[8],zmm0[8],zmm3[9],zmm0[9],zmm3[12],zmm0[12],zmm3[13],zmm0[13]
+; UNPCK-NEXT: vpaddd %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm2 = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
+; UNPCK-NEXT: vpaddd %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %eax
+; UNPCK-NEXT: vpextrd $3, %xmm0, %ecx
+; UNPCK-NEXT: imull %eax, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %edx
+; UNPCK-NEXT: vpextrd $2, %xmm0, %eax
+; UNPCK-NEXT: imull %edx, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i32_512_n4:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm4
+; BASE-NEXT: vpaddd %zmm4, %zmm0, %zmm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm4
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm4 = xmm0[1,1,1,1]
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm0
+; BASE-NEXT: vpaddd %zmm0, %zmm1, %zmm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: imull %eax, %ecx
+; BASE-NEXT: vextracti64x4 $1, %zmm2, %ymm0
+; BASE-NEXT: vpaddd %zmm0, %zmm2, %zmm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %edx
+; BASE-NEXT: vextracti64x4 $1, %zmm3, %ymm0
+; BASE-NEXT: vpaddd %zmm0, %zmm3, %zmm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: imull %edx, %eax
+; BASE-NEXT: imull %ecx, %eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %b)
+ %rc = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %c)
+ %rd = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %d)
+ %m0 = mul i32 %ra, %rb
+ %m1 = mul i32 %m0, %rc
+ %r = mul i32 %m1, %rd
+ ret i32 %r
+}
+
+; i32/256, N=4.
+define i32 @add_i32_256_n4(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
+; UNPCK-LABEL: add_i32_256_n4:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} ymm4 = ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[6],ymm2[6],ymm1[7],ymm2[7]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[4],ymm2[4],ymm1[5],ymm2[5]
+; UNPCK-NEXT: vpaddd %ymm4, %ymm1, %ymm1
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm3[2],ymm0[2],ymm3[3],ymm0[3],ymm3[6],ymm0[6],ymm3[7],ymm0[7]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm3[0],ymm0[0],ymm3[1],ymm0[1],ymm3[4],ymm0[4],ymm3[5],ymm0[5]
+; UNPCK-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
+; UNPCK-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %eax
+; UNPCK-NEXT: vpextrd $3, %xmm0, %ecx
+; UNPCK-NEXT: imull %eax, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %edx
+; UNPCK-NEXT: vpextrd $2, %xmm0, %eax
+; UNPCK-NEXT: imull %edx, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i32_256_n4:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm4
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/209963
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