[llvm] [RISCV] coalesce between VSETVLI and SF_VSETTNT (PR #203438)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 15 21:18:59 PDT 2026
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/203438
>From d1afa1aed482e74f4997d9342eaef32c3b493e19 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 11 Jun 2026 19:12:35 -0700
Subject: [PATCH 1/8] [RISCV] precommit test
---
.../CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll | 711 ++++++++++++++++++
1 file changed, 711 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll b/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
new file mode 100644
index 0000000000000..5278d57fc41d0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
@@ -0,0 +1,711 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+xsfmmbase,+xsfmm32a,+xsfmm32a8f,+xsfmm64a64f | FileCheck %s
+; RUN: llc < %s -mcpu=sifive-x280 -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+xsfmmbase,+xsfmm32a,+xsfmm32a8f,+xsfmm64a64f | FileCheck %s -check-prefix=X280
+
+define void @matmulf16(i64 noundef %ATM, i64 noundef %ATN, i64 noundef %ATK, ptr noundef readonly captures(none) %a, i64 noundef %lda, ptr noundef readonly captures(none) %b, i64 noundef %ldb, ptr noundef writeonly captures(none) %c, i64 noundef %ldc) nounwind {
+; CHECK-LABEL: matmulf16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi sp, sp, -144
+; CHECK-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 128(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s1, 120(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s2, 112(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s3, 104(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s4, 96(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s5, 88(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s6, 80(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s7, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s8, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s9, 56(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s10, 48(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s11, 40(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd a7, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd a3, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT: beqz a0, .LBB0_14
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: mv s4, a1
+; CHECK-NEXT: beqz a1, .LBB0_14
+; CHECK-NEXT: # %bb.2: # %for.body6.lr.ph.preheader
+; CHECK-NEXT: mv s1, a5
+; CHECK-NEXT: mv s7, a2
+; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: ld s6, 144(sp)
+; CHECK-NEXT: slli s8, a4, 2
+; CHECK-NEXT: slli s9, a4, 1
+; CHECK-NEXT: slli s10, a6, 2
+; CHECK-NEXT: slli s11, a6, 1
+; CHECK-NEXT: slli s6, s6, 1
+; CHECK-NEXT: li s0, 2
+; CHECK-NEXT: li s3, 1
+; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: j .LBB0_4
+; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup5
+; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=1
+; CHECK-NEXT: ld a2, 32(sp) # 8-byte Folded Reload
+; CHECK-NEXT: add a2, s5, a2
+; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: bgeu a2, a0, .LBB0_13
+; CHECK-NEXT: .LBB0_4: # %for.body6.lr.ph
+; CHECK-NEXT: # =>This Loop Header: Depth=1
+; CHECK-NEXT: # Child Loop BB0_6 Depth 2
+; CHECK-NEXT: # Child Loop BB0_7 Depth 3
+; CHECK-NEXT: # Child Loop BB0_12 Depth 3
+; CHECK-NEXT: sub a0, a0, a2
+; CHECK-NEXT: slli s2, a2, 1
+; CHECK-NEXT: sf.vsettnt a1, zero, e16, w2
+; CHECK-NEXT: sf.vsettm s5, a0
+; CHECK-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT: add s2, a0, s2
+; CHECK-NEXT: sd a2, 32(sp) # 8-byte Folded Spill
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: ld a1, 144(sp)
+; CHECK-NEXT: call __muldi3
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: ld a2, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT: add a0, a2, a0
+; CHECK-NEXT: j .LBB0_6
+; CHECK-NEXT: .LBB0_5: # %for.cond.cleanup28
+; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: bgeu a1, s4, .LBB0_3
+; CHECK-NEXT: .LBB0_6: # %for.body6
+; CHECK-NEXT: # Parent Loop BB0_4 Depth=1
+; CHECK-NEXT: # => This Loop Header: Depth=2
+; CHECK-NEXT: # Child Loop BB0_7 Depth 3
+; CHECK-NEXT: # Child Loop BB0_12 Depth 3
+; CHECK-NEXT: sub a2, s4, a1
+; CHECK-NEXT: sf.vsettnt a2, a2, e16, w2
+; CHECK-NEXT: slli a3, a1, 1
+; CHECK-NEXT: sf.vsettnt zero, zero, e16, w2
+; CHECK-NEXT: sf.vsettm zero, s5
+; CHECK-NEXT: sf.vtzero.t mt0
+; CHECK-NEXT: add a4, s1, a3
+; CHECK-NEXT: mv a5, s2
+; CHECK-NEXT: bltu s7, s0, .LBB0_8
+; CHECK-NEXT: .LBB0_7: # %while.body
+; CHECK-NEXT: # Parent Loop BB0_4 Depth=1
+; CHECK-NEXT: # Parent Loop BB0_6 Depth=2
+; CHECK-NEXT: # => This Inner Loop Header: Depth=3
+; CHECK-NEXT: vsetvli zero, s5, e16, m4, ta, ma
+; CHECK-NEXT: vle16.v v8, (a5)
+; CHECK-NEXT: add a6, a5, s9
+; CHECK-NEXT: vle16.v v12, (a6)
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vle16.v v16, (a4)
+; CHECK-NEXT: add a6, a4, s11
+; CHECK-NEXT: vle16.v v20, (a6)
+; CHECK-NEXT: sf.vsettnt zero, a2, e16, w2
+; CHECK-NEXT: sf.vsettk a6, s7
+; CHECK-NEXT: sf.vsettm zero, s5
+; CHECK-NEXT: sf.vsettk zero, a6
+; CHECK-NEXT: sf.mm.f.f mt0, v8, v16
+; CHECK-NEXT: sub s7, s7, a6
+; CHECK-NEXT: add a5, a5, s8
+; CHECK-NEXT: add a4, a4, s10
+; CHECK-NEXT: bltu s3, s7, .LBB0_7
+; CHECK-NEXT: .LBB0_8: # %while.end
+; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
+; CHECK-NEXT: beqz s7, .LBB0_10
+; CHECK-NEXT: # %bb.9: # %if.then18
+; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
+; CHECK-NEXT: vsetvli zero, s5, e16, m8, ta, ma
+; CHECK-NEXT: vle16.v v8, (a5)
+; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; CHECK-NEXT: vle16.v v16, (a4)
+; CHECK-NEXT: sf.vsettnt zero, a2, e16, w2
+; CHECK-NEXT: sf.vsettk a4, s3
+; CHECK-NEXT: sf.vsettm zero, s5
+; CHECK-NEXT: sf.vsettk zero, a4
+; CHECK-NEXT: sf.mm.f.f mt0, v8, v16
+; CHECK-NEXT: sub s7, s3, a4
+; CHECK-NEXT: .LBB0_10: # %if.end25
+; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
+; CHECK-NEXT: beqz s5, .LBB0_5
+; CHECK-NEXT: # %bb.11: # %for.body29.preheader
+; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
+; CHECK-NEXT: li a4, 0
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: .LBB0_12: # %for.body29
+; CHECK-NEXT: # Parent Loop BB0_4 Depth=1
+; CHECK-NEXT: # Parent Loop BB0_6 Depth=2
+; CHECK-NEXT: # => This Inner Loop Header: Depth=3
+; CHECK-NEXT: sf.vsettnt zero, a2, e32, w1
+; CHECK-NEXT: sf.vtmv.v.t v8, a4
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfncvt.f.f.w v16, v8
+; CHECK-NEXT: addi a4, a4, 1
+; CHECK-NEXT: vse16.v v16, (a3)
+; CHECK-NEXT: add a3, a3, s6
+; CHECK-NEXT: bne s5, a4, .LBB0_12
+; CHECK-NEXT: j .LBB0_5
+; CHECK-NEXT: .LBB0_13: # %for.cond.cleanup
+; CHECK-NEXT: sf.vtdiscard
+; CHECK-NEXT: .LBB0_14: # %return
+; CHECK-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s1, 120(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s2, 112(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s3, 104(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s4, 96(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s5, 88(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s6, 80(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s7, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s8, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s9, 56(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s10, 48(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s11, 40(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 144
+; CHECK-NEXT: ret
+;
+; X280-LABEL: matmulf16:
+; X280: # %bb.0: # %entry
+; X280-NEXT: beqz a0, .LBB0_14
+; X280-NEXT: # %bb.1: # %entry
+; X280-NEXT: beqz a1, .LBB0_14
+; X280-NEXT: # %bb.2: # %for.body6.lr.ph.preheader
+; X280-NEXT: addi sp, sp, -80
+; X280-NEXT: ld t2, 80(sp)
+; X280-NEXT: li t0, 0
+; X280-NEXT: slli t1, a4, 2
+; X280-NEXT: slli a4, a4, 1
+; X280-NEXT: slli t3, a6, 2
+; X280-NEXT: slli a6, a6, 1
+; X280-NEXT: slli t4, t2, 1
+; X280-NEXT: li t5, 2
+; X280-NEXT: li t6, 1
+; X280-NEXT: sd s0, 72(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s1, 64(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s2, 56(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s3, 48(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s4, 40(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s5, 32(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s6, 24(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s7, 16(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s8, 8(sp) # 8-byte Folded Spill
+; X280-NEXT: j .LBB0_4
+; X280-NEXT: .LBB0_3: # %for.cond.cleanup5
+; X280-NEXT: # in Loop: Header=BB0_4 Depth=1
+; X280-NEXT: add t0, t0, s2
+; X280-NEXT: bgeu t0, a0, .LBB0_13
+; X280-NEXT: .LBB0_4: # %for.body6.lr.ph
+; X280-NEXT: # =>This Loop Header: Depth=1
+; X280-NEXT: # Child Loop BB0_6 Depth 2
+; X280-NEXT: # Child Loop BB0_7 Depth 3
+; X280-NEXT: # Child Loop BB0_12 Depth 3
+; X280-NEXT: sf.vsettnt s3, zero, e16, w2
+; X280-NEXT: sub s2, a0, t0
+; X280-NEXT: mul s3, t0, t2
+; X280-NEXT: li s0, 0
+; X280-NEXT: sh1add s1, t0, a3
+; X280-NEXT: sf.vsettm s2, s2
+; X280-NEXT: sh1add s3, s3, a7
+; X280-NEXT: j .LBB0_6
+; X280-NEXT: .LBB0_5: # %for.cond.cleanup28
+; X280-NEXT: # in Loop: Header=BB0_6 Depth=2
+; X280-NEXT: add s0, s0, s4
+; X280-NEXT: bgeu s0, a1, .LBB0_3
+; X280-NEXT: .LBB0_6: # %for.body6
+; X280-NEXT: # Parent Loop BB0_4 Depth=1
+; X280-NEXT: # => This Loop Header: Depth=2
+; X280-NEXT: # Child Loop BB0_7 Depth 3
+; X280-NEXT: # Child Loop BB0_12 Depth 3
+; X280-NEXT: sub s4, a1, s0
+; X280-NEXT: sh1add s5, s0, a5
+; X280-NEXT: sf.vsettnt s4, s4, e16, w2
+; X280-NEXT: mv s6, s1
+; X280-NEXT: sf.vsettnt zero, zero, e16, w2
+; X280-NEXT: sf.vsettm zero, s2
+; X280-NEXT: sf.vtzero.t mt0
+; X280-NEXT: bltu a2, t5, .LBB0_8
+; X280-NEXT: .LBB0_7: # %while.body
+; X280-NEXT: # Parent Loop BB0_4 Depth=1
+; X280-NEXT: # Parent Loop BB0_6 Depth=2
+; X280-NEXT: # => This Inner Loop Header: Depth=3
+; X280-NEXT: add s7, s6, a4
+; X280-NEXT: vsetvli zero, s2, e16, m4, ta, ma
+; X280-NEXT: vle16.v v8, (s6)
+; X280-NEXT: add s6, s6, t1
+; X280-NEXT: vle16.v v12, (s7)
+; X280-NEXT: vsetvli zero, s4, e16, m4, ta, ma
+; X280-NEXT: add s7, s5, a6
+; X280-NEXT: vle16.v v16, (s5)
+; X280-NEXT: sf.vsettnt zero, s4, e16, w2
+; X280-NEXT: sf.vsettk s8, a2
+; X280-NEXT: add s5, s5, t3
+; X280-NEXT: vsetvli zero, s4, e16, m4, ta, ma
+; X280-NEXT: sub a2, a2, s8
+; X280-NEXT: vle16.v v20, (s7)
+; X280-NEXT: sf.vsettnt zero, s4, e16, w2
+; X280-NEXT: sf.vsettm zero, s2
+; X280-NEXT: sf.vsettk zero, s8
+; X280-NEXT: sf.mm.f.f mt0, v8, v16
+; X280-NEXT: bltu t6, a2, .LBB0_7
+; X280-NEXT: .LBB0_8: # %while.end
+; X280-NEXT: # in Loop: Header=BB0_6 Depth=2
+; X280-NEXT: beqz a2, .LBB0_10
+; X280-NEXT: # %bb.9: # %if.then18
+; X280-NEXT: # in Loop: Header=BB0_6 Depth=2
+; X280-NEXT: vsetvli zero, s2, e16, m8, ta, ma
+; X280-NEXT: vle16.v v8, (s6)
+; X280-NEXT: sf.vsettnt zero, s2, e16, w2
+; X280-NEXT: sf.vsettk s6, t6
+; X280-NEXT: vsetvli zero, s4, e16, m8, ta, ma
+; X280-NEXT: sub a2, t6, s6
+; X280-NEXT: vle16.v v16, (s5)
+; X280-NEXT: sf.vsettnt zero, s4, e16, w2
+; X280-NEXT: sf.vsettm zero, s2
+; X280-NEXT: sf.vsettk zero, s6
+; X280-NEXT: sf.mm.f.f mt0, v8, v16
+; X280-NEXT: .LBB0_10: # %if.end25
+; X280-NEXT: # in Loop: Header=BB0_6 Depth=2
+; X280-NEXT: beqz s2, .LBB0_5
+; X280-NEXT: # %bb.11: # %for.body29.preheader
+; X280-NEXT: # in Loop: Header=BB0_6 Depth=2
+; X280-NEXT: li s5, 0
+; X280-NEXT: sh1add s6, s0, s3
+; X280-NEXT: .LBB0_12: # %for.body29
+; X280-NEXT: # Parent Loop BB0_4 Depth=1
+; X280-NEXT: # Parent Loop BB0_6 Depth=2
+; X280-NEXT: # => This Inner Loop Header: Depth=3
+; X280-NEXT: sf.vsettnt zero, s4, e32, w1
+; X280-NEXT: sf.vtmv.v.t v8, s5
+; X280-NEXT: vsetvli zero, s4, e16, m4, ta, ma
+; X280-NEXT: vfncvt.f.f.w v16, v8
+; X280-NEXT: addi s5, s5, 1
+; X280-NEXT: vse16.v v16, (s6)
+; X280-NEXT: add s6, s6, t4
+; X280-NEXT: bne s2, s5, .LBB0_12
+; X280-NEXT: j .LBB0_5
+; X280-NEXT: .LBB0_13: # %for.cond.cleanup
+; X280-NEXT: sf.vtdiscard
+; X280-NEXT: ld s0, 72(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s1, 64(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s2, 56(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s3, 48(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s4, 40(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s5, 32(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s6, 24(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s7, 16(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s8, 8(sp) # 8-byte Folded Reload
+; X280-NEXT: addi sp, sp, 80
+; X280-NEXT: .LBB0_14: # %return
+; X280-NEXT: ret
+entry:
+ %cmp = icmp eq i64 %ATM, 0
+ %cmp1 = icmp eq i64 %ATN, 0
+ %or.cond = or i1 %cmp, %cmp1
+ br i1 %or.cond, label %return, label %for.body6.lr.ph
+
+for.cond.cleanup: ; preds = %for.cond.cleanup5
+ tail call void @llvm.riscv.sf.vtdiscard()
+ br label %return
+
+for.body6.lr.ph: ; preds = %entry, %for.cond.cleanup5
+ %ATK.addr.0105 = phi i64 [ %ATK.addr.3, %for.cond.cleanup5 ], [ %ATK, %entry ]
+ %m.0104 = phi i64 [ %add35, %for.cond.cleanup5 ], [ 0, %entry ]
+ %sub = sub nuw i64 %ATM, %m.0104
+ %0 = tail call i64 @llvm.riscv.sf.vsettm.i64(i64 %sub, i64 1, i64 2)
+ %add.ptr = getelementptr inbounds nuw half, ptr %a, i64 %m.0104
+ %mul = mul i64 %m.0104, %ldc
+ %add.ptr9 = getelementptr inbounds nuw half, ptr %c, i64 %mul
+ %cmp2796.not = icmp eq i64 %0, 0
+ br label %for.body6
+
+for.cond.cleanup5: ; preds = %for.cond.cleanup28
+ %add35 = add i64 %0, %m.0104
+ %cmp2 = icmp ult i64 %add35, %ATM
+ br i1 %cmp2, label %for.body6.lr.ph, label %for.cond.cleanup
+
+for.body6: ; preds = %for.body6.lr.ph, %for.cond.cleanup28
+ %ATK.addr.1102 = phi i64 [ %ATK.addr.0105, %for.body6.lr.ph ], [ %ATK.addr.3, %for.cond.cleanup28 ]
+ %n.0101 = phi i64 [ 0, %for.body6.lr.ph ], [ %add, %for.cond.cleanup28 ]
+ %sub7 = sub nuw i64 %ATN, %n.0101
+ %1 = tail call i64 @llvm.riscv.sf.vsettnt.i64(i64 %sub7, i64 1, i64 2)
+ tail call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2)
+ %add.ptr8 = getelementptr inbounds nuw half, ptr %b, i64 %n.0101
+ %add.ptr10 = getelementptr inbounds nuw half, ptr %add.ptr9, i64 %n.0101
+ %cmp1190 = icmp ugt i64 %ATK.addr.1102, 1
+ br i1 %cmp1190, label %while.body, label %while.end
+
+while.body: ; preds = %for.body6, %while.body
+ %ATK.addr.293 = phi i64 [ %sub16, %while.body ], [ %ATK.addr.1102, %for.body6 ]
+ %a0.092 = phi ptr [ %add.ptr13, %while.body ], [ %add.ptr, %for.body6 ]
+ %b0.091 = phi ptr [ %add.ptr15, %while.body ], [ %add.ptr8, %for.body6 ]
+ %2 = tail call i64 @llvm.riscv.sf.vsettk.i64(i64 %ATK.addr.293, i64 1, i64 2)
+ %3 = tail call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.i64(<vscale x 16 x half> poison, ptr %a0.092, i64 %0)
+ %add.ptr12 = getelementptr inbounds nuw half, ptr %a0.092, i64 %lda
+ %4 = tail call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.i64(<vscale x 16 x half> poison, ptr %add.ptr12, i64 %0)
+ %add.ptr13 = getelementptr inbounds nuw half, ptr %add.ptr12, i64 %lda
+ %5 = tail call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> poison, <vscale x 16 x half> %3, i64 0)
+ %6 = tail call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %5, <vscale x 16 x half> %4, i64 16)
+ %7 = tail call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.i64(<vscale x 16 x half> poison, ptr %b0.091, i64 %1)
+ %add.ptr14 = getelementptr inbounds nuw half, ptr %b0.091, i64 %ldb
+ %8 = tail call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.i64(<vscale x 16 x half> poison, ptr %add.ptr14, i64 %1)
+ %add.ptr15 = getelementptr inbounds nuw half, ptr %add.ptr14, i64 %ldb
+ %9 = tail call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> poison, <vscale x 16 x half> %7, i64 0)
+ %10 = tail call <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> %9, <vscale x 16 x half> %8, i64 16)
+ tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %6, <vscale x 32 x half> %10, i64 %0, i64 %1, i64 %2, i64 2)
+ %sub16 = sub i64 %ATK.addr.293, %2
+ %cmp11 = icmp ugt i64 %sub16, 1
+ br i1 %cmp11, label %while.body, label %while.end
+
+while.end: ; preds = %while.body, %for.body6
+ %b0.0.lcssa = phi ptr [ %add.ptr8, %for.body6 ], [ %add.ptr15, %while.body ]
+ %a0.0.lcssa = phi ptr [ %add.ptr, %for.body6 ], [ %add.ptr13, %while.body ]
+ %ATK.addr.2.lcssa = phi i64 [ %ATK.addr.1102, %for.body6 ], [ %sub16, %while.body ]
+ %cmp17.not = icmp eq i64 %ATK.addr.2.lcssa, 0
+ br i1 %cmp17.not, label %if.end25, label %if.then18
+
+if.then18: ; preds = %while.end
+ %11 = tail call i64 @llvm.riscv.sf.vsettk.i64(i64 1, i64 1, i64 2)
+ %12 = tail call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.i64(<vscale x 32 x half> poison, ptr %a0.0.lcssa, i64 %0)
+ %13 = tail call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.i64(<vscale x 32 x half> poison, ptr %b0.0.lcssa, i64 %1)
+ tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %12, <vscale x 32 x half> %13, i64 %0, i64 %1, i64 %11, i64 2)
+ %sub24 = sub i64 1, %11
+ br label %if.end25
+
+if.end25: ; preds = %if.then18, %while.end
+ %ATK.addr.3 = phi i64 [ %sub24, %if.then18 ], [ 0, %while.end ]
+ br i1 %cmp2796.not, label %for.cond.cleanup28, label %for.body29
+
+for.cond.cleanup28: ; preds = %for.body29, %if.end25
+ %add = add i64 %1, %n.0101
+ %cmp4 = icmp ult i64 %add, %ATN
+ br i1 %cmp4, label %for.body6, label %for.cond.cleanup5
+
+for.body29: ; preds = %if.end25, %for.body29
+ %c00.099 = phi ptr [ %add.ptr31, %for.body29 ], [ %add.ptr10, %if.end25 ]
+ %tss.098 = phi i64 [ %inc30, %for.body29 ], [ 0, %if.end25 ]
+ %14 = tail call <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %tss.098, i64 %1)
+ %15 = tail call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> %14, i64 7, i64 %1)
+ tail call void @llvm.riscv.vse.nxv16f16.i64(<vscale x 16 x half> %15, ptr %c00.099, i64 %1)
+ %inc30 = add nuw i64 %tss.098, 1
+ %add.ptr31 = getelementptr inbounds nuw half, ptr %c00.099, i64 %ldc
+ %exitcond.not = icmp eq i64 %inc30, %0
+ br i1 %exitcond.not, label %for.cond.cleanup28, label %for.body29
+
+return: ; preds = %entry, %for.cond.cleanup
+ ret void
+}
+
+define void @matmul32(i64 noundef %ATM, i64 noundef %ATN, i64 noundef %ATK, ptr noundef readonly captures(none) %a, i64 noundef %lda, ptr noundef readonly captures(none) %b, i64 noundef %ldb, ptr noundef writeonly captures(none) %c, i64 noundef %ldc) nounwind {
+; CHECK-LABEL: matmul32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi sp, sp, -112
+; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: beqz a0, .LBB1_13
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: mv s5, a1
+; CHECK-NEXT: beqz a1, .LBB1_13
+; CHECK-NEXT: # %bb.2: # %for.cond.preheader
+; CHECK-NEXT: mv s0, a7
+; CHECK-NEXT: mv s1, a5
+; CHECK-NEXT: mv s2, a0
+; CHECK-NEXT: mv s7, a3
+; CHECK-NEXT: mv s4, a2
+; CHECK-NEXT: li s6, 0
+; CHECK-NEXT: ld s10, 112(sp)
+; CHECK-NEXT: slli s8, a6, 2
+; CHECK-NEXT: slli s9, a4, 2
+; CHECK-NEXT: slli s10, s10, 2
+; CHECK-NEXT: j .LBB1_4
+; CHECK-NEXT: .LBB1_3: # %for.cond.cleanup5
+; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1
+; CHECK-NEXT: add s6, s11, s6
+; CHECK-NEXT: bgeu s6, s2, .LBB1_12
+; CHECK-NEXT: .LBB1_4: # %for.body6.lr.ph
+; CHECK-NEXT: # =>This Loop Header: Depth=1
+; CHECK-NEXT: # Child Loop BB1_6 Depth 2
+; CHECK-NEXT: # Child Loop BB1_8 Depth 3
+; CHECK-NEXT: # Child Loop BB1_11 Depth 3
+; CHECK-NEXT: sub a0, s2, s6
+; CHECK-NEXT: slli s3, s6, 2
+; CHECK-NEXT: sf.vsettnt a1, zero, e32, w1
+; CHECK-NEXT: sf.vsettm s11, a0
+; CHECK-NEXT: add s3, s7, s3
+; CHECK-NEXT: mv a0, s6
+; CHECK-NEXT: ld a1, 112(sp)
+; CHECK-NEXT: call __muldi3
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: add a0, s0, a0
+; CHECK-NEXT: j .LBB1_6
+; CHECK-NEXT: .LBB1_5: # %for.cond.cleanup20
+; CHECK-NEXT: # in Loop: Header=BB1_6 Depth=2
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: bgeu a1, s5, .LBB1_3
+; CHECK-NEXT: .LBB1_6: # %for.body6
+; CHECK-NEXT: # Parent Loop BB1_4 Depth=1
+; CHECK-NEXT: # => This Loop Header: Depth=2
+; CHECK-NEXT: # Child Loop BB1_8 Depth 3
+; CHECK-NEXT: # Child Loop BB1_11 Depth 3
+; CHECK-NEXT: sub a2, s5, a1
+; CHECK-NEXT: sf.vsettnt a2, a2, e32, w1
+; CHECK-NEXT: sf.vsettnt zero, zero, e32, w1
+; CHECK-NEXT: sf.vsettm zero, s11
+; CHECK-NEXT: sf.vtzero.t mt0
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: beqz s4, .LBB1_9
+; CHECK-NEXT: # %bb.7: # %for.body14.preheader
+; CHECK-NEXT: # in Loop: Header=BB1_6 Depth=2
+; CHECK-NEXT: li a4, 0
+; CHECK-NEXT: add a5, s1, a3
+; CHECK-NEXT: mv a6, s3
+; CHECK-NEXT: .LBB1_8: # %for.body14
+; CHECK-NEXT: # Parent Loop BB1_4 Depth=1
+; CHECK-NEXT: # Parent Loop BB1_6 Depth=2
+; CHECK-NEXT: # => This Inner Loop Header: Depth=3
+; CHECK-NEXT: vsetvli zero, s11, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v8, (a6)
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v16, (a5)
+; CHECK-NEXT: sub a7, s4, a4
+; CHECK-NEXT: sf.vsettnt zero, a2, e32, w1
+; CHECK-NEXT: sf.vsettk a7, a7
+; CHECK-NEXT: sf.vsettm zero, s11
+; CHECK-NEXT: sf.vsettk zero, a7
+; CHECK-NEXT: sf.mm.f.f mt0, v8, v16
+; CHECK-NEXT: add a4, a7, a4
+; CHECK-NEXT: add a5, a5, s8
+; CHECK-NEXT: add a6, a6, s9
+; CHECK-NEXT: bltu a4, s4, .LBB1_8
+; CHECK-NEXT: .LBB1_9: # %for.cond18.preheader
+; CHECK-NEXT: # in Loop: Header=BB1_6 Depth=2
+; CHECK-NEXT: beqz s11, .LBB1_5
+; CHECK-NEXT: # %bb.10: # %for.body21.preheader
+; CHECK-NEXT: # in Loop: Header=BB1_6 Depth=2
+; CHECK-NEXT: li a4, 0
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: .LBB1_11: # %for.body21
+; CHECK-NEXT: # Parent Loop BB1_4 Depth=1
+; CHECK-NEXT: # Parent Loop BB1_6 Depth=2
+; CHECK-NEXT: # => This Inner Loop Header: Depth=3
+; CHECK-NEXT: sf.vste32 a4, (a3)
+; CHECK-NEXT: addi a4, a4, 1
+; CHECK-NEXT: add a3, a3, s10
+; CHECK-NEXT: bne s11, a4, .LBB1_11
+; CHECK-NEXT: j .LBB1_5
+; CHECK-NEXT: .LBB1_12: # %for.cond.cleanup
+; CHECK-NEXT: sf.vtdiscard
+; CHECK-NEXT: .LBB1_13: # %return
+; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 112
+; CHECK-NEXT: ret
+;
+; X280-LABEL: matmul32:
+; X280: # %bb.0: # %entry
+; X280-NEXT: beqz a0, .LBB1_13
+; X280-NEXT: # %bb.1: # %entry
+; X280-NEXT: beqz a1, .LBB1_13
+; X280-NEXT: # %bb.2: # %for.cond.preheader
+; X280-NEXT: addi sp, sp, -48
+; X280-NEXT: ld t1, 48(sp)
+; X280-NEXT: li t0, 0
+; X280-NEXT: slli a6, a6, 2
+; X280-NEXT: slli a4, a4, 2
+; X280-NEXT: slli t2, t1, 2
+; X280-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s2, 24(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s3, 16(sp) # 8-byte Folded Spill
+; X280-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
+; X280-NEXT: j .LBB1_4
+; X280-NEXT: .LBB1_3: # %for.cond.cleanup5
+; X280-NEXT: # in Loop: Header=BB1_4 Depth=1
+; X280-NEXT: add t0, t0, t5
+; X280-NEXT: bgeu t0, a0, .LBB1_12
+; X280-NEXT: .LBB1_4: # %for.body6.lr.ph
+; X280-NEXT: # =>This Loop Header: Depth=1
+; X280-NEXT: # Child Loop BB1_6 Depth 2
+; X280-NEXT: # Child Loop BB1_8 Depth 3
+; X280-NEXT: # Child Loop BB1_11 Depth 3
+; X280-NEXT: sf.vsettnt t6, zero, e32, w1
+; X280-NEXT: sub t5, a0, t0
+; X280-NEXT: mul t6, t0, t1
+; X280-NEXT: li t3, 0
+; X280-NEXT: sh2add t4, t0, a3
+; X280-NEXT: sf.vsettm t5, t5
+; X280-NEXT: sh2add t6, t6, a7
+; X280-NEXT: j .LBB1_6
+; X280-NEXT: .LBB1_5: # %for.cond.cleanup20
+; X280-NEXT: # in Loop: Header=BB1_6 Depth=2
+; X280-NEXT: add t3, t3, s0
+; X280-NEXT: bgeu t3, a1, .LBB1_3
+; X280-NEXT: .LBB1_6: # %for.body6
+; X280-NEXT: # Parent Loop BB1_4 Depth=1
+; X280-NEXT: # => This Loop Header: Depth=2
+; X280-NEXT: # Child Loop BB1_8 Depth 3
+; X280-NEXT: # Child Loop BB1_11 Depth 3
+; X280-NEXT: sub s0, a1, t3
+; X280-NEXT: sf.vsettnt s0, s0, e32, w1
+; X280-NEXT: sf.vsettnt zero, zero, e32, w1
+; X280-NEXT: sf.vsettm zero, t5
+; X280-NEXT: sf.vtzero.t mt0
+; X280-NEXT: beqz a2, .LBB1_9
+; X280-NEXT: # %bb.7: # %for.body14.preheader
+; X280-NEXT: # in Loop: Header=BB1_6 Depth=2
+; X280-NEXT: li s1, 0
+; X280-NEXT: sh2add s2, t3, a5
+; X280-NEXT: mv s3, t4
+; X280-NEXT: .LBB1_8: # %for.body14
+; X280-NEXT: # Parent Loop BB1_4 Depth=1
+; X280-NEXT: # Parent Loop BB1_6 Depth=2
+; X280-NEXT: # => This Inner Loop Header: Depth=3
+; X280-NEXT: vsetvli zero, t5, e32, m8, ta, ma
+; X280-NEXT: vle32.v v8, (s3)
+; X280-NEXT: sub s4, a2, s1
+; X280-NEXT: add s3, s3, a4
+; X280-NEXT: sf.vsettnt zero, t5, e32, w1
+; X280-NEXT: sf.vsettk s4, s4
+; X280-NEXT: vsetvli zero, s0, e32, m8, ta, ma
+; X280-NEXT: add s1, s1, s4
+; X280-NEXT: vle32.v v16, (s2)
+; X280-NEXT: add s2, s2, a6
+; X280-NEXT: sf.vsettnt zero, s0, e32, w1
+; X280-NEXT: sf.vsettm zero, t5
+; X280-NEXT: sf.vsettk zero, s4
+; X280-NEXT: sf.mm.f.f mt0, v8, v16
+; X280-NEXT: bltu s1, a2, .LBB1_8
+; X280-NEXT: .LBB1_9: # %for.cond18.preheader
+; X280-NEXT: # in Loop: Header=BB1_6 Depth=2
+; X280-NEXT: beqz t5, .LBB1_5
+; X280-NEXT: # %bb.10: # %for.body21.preheader
+; X280-NEXT: # in Loop: Header=BB1_6 Depth=2
+; X280-NEXT: li s1, 0
+; X280-NEXT: sh2add s2, t3, t6
+; X280-NEXT: .LBB1_11: # %for.body21
+; X280-NEXT: # Parent Loop BB1_4 Depth=1
+; X280-NEXT: # Parent Loop BB1_6 Depth=2
+; X280-NEXT: # => This Inner Loop Header: Depth=3
+; X280-NEXT: sf.vste32 s1, (s2)
+; X280-NEXT: add s2, s2, t2
+; X280-NEXT: addi s1, s1, 1
+; X280-NEXT: bne t5, s1, .LBB1_11
+; X280-NEXT: j .LBB1_5
+; X280-NEXT: .LBB1_12: # %for.cond.cleanup
+; X280-NEXT: sf.vtdiscard
+; X280-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s2, 24(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s3, 16(sp) # 8-byte Folded Reload
+; X280-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
+; X280-NEXT: addi sp, sp, 48
+; X280-NEXT: .LBB1_13: # %return
+; X280-NEXT: ret
+entry:
+ %cmp = icmp eq i64 %ATM, 0
+ %cmp1 = icmp eq i64 %ATN, 0
+ %or.cond = or i1 %cmp, %cmp1
+ br i1 %or.cond, label %return, label %for.cond.preheader
+
+for.cond.preheader: ; preds = %entry
+ %cmp1262.not = icmp eq i64 %ATK, 0
+ br label %for.body6.lr.ph
+
+for.cond.cleanup: ; preds = %for.cond.cleanup5
+ tail call void @llvm.riscv.sf.vtdiscard()
+ br label %return
+
+for.body6.lr.ph: ; preds = %for.cond.cleanup5, %for.cond.preheader
+ %m.072 = phi i64 [ 0, %for.cond.preheader ], [ %add30, %for.cond.cleanup5 ]
+ %sub = sub nuw i64 %ATM, %m.072
+ %0 = tail call i64 @llvm.riscv.sf.vsettm.i64(i64 %sub, i64 2, i64 1)
+ %add.ptr = getelementptr inbounds nuw float, ptr %a, i64 %m.072
+ %mul = mul i64 %m.072, %ldc
+ %add.ptr9 = getelementptr inbounds nuw float, ptr %c, i64 %mul
+ %cmp1966.not = icmp eq i64 %0, 0
+ br label %for.body6
+
+for.cond.cleanup5: ; preds = %for.cond.cleanup20
+ %add30 = add i64 %0, %m.072
+ %cmp2 = icmp ult i64 %add30, %ATM
+ br i1 %cmp2, label %for.body6.lr.ph, label %for.cond.cleanup
+
+for.body6: ; preds = %for.body6.lr.ph, %for.cond.cleanup20
+ %n.071 = phi i64 [ 0, %for.body6.lr.ph ], [ %add27, %for.cond.cleanup20 ]
+ %sub7 = sub nuw i64 %ATN, %n.071
+ %1 = tail call i64 @llvm.riscv.sf.vsettnt.i64(i64 %sub7, i64 2, i64 1)
+ tail call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1)
+ %add.ptr10 = getelementptr inbounds nuw float, ptr %add.ptr9, i64 %n.071
+ br i1 %cmp1262.not, label %for.cond18.preheader, label %for.body14.preheader
+
+for.body14.preheader: ; preds = %for.body6
+ %add.ptr8 = getelementptr inbounds nuw float, ptr %b, i64 %n.071
+ br label %for.body14
+
+for.cond18.preheader: ; preds = %for.body14, %for.body6
+ br i1 %cmp1966.not, label %for.cond.cleanup20, label %for.body21
+
+for.body14: ; preds = %for.body14.preheader, %for.body14
+ %k.065 = phi i64 [ %add, %for.body14 ], [ 0, %for.body14.preheader ]
+ %b0.064 = phi ptr [ %add.ptr17, %for.body14 ], [ %add.ptr8, %for.body14.preheader ]
+ %a0.063 = phi ptr [ %add.ptr16, %for.body14 ], [ %add.ptr, %for.body14.preheader ]
+ %sub15 = sub nuw i64 %ATK, %k.065
+ %2 = tail call i64 @llvm.riscv.sf.vsettk.i64(i64 %sub15, i64 2, i64 1)
+ %3 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float> poison, ptr %a0.063, i64 %0)
+ %add.ptr16 = getelementptr inbounds nuw float, ptr %a0.063, i64 %lda
+ %4 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float> poison, ptr %b0.064, i64 %1)
+ %add.ptr17 = getelementptr inbounds nuw float, ptr %b0.064, i64 %ldb
+ tail call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> %3, <vscale x 16 x float> %4, i64 %0, i64 %1, i64 %2, i64 1)
+ %add = add i64 %2, %k.065
+ %cmp12 = icmp ult i64 %add, %ATK
+ br i1 %cmp12, label %for.body14, label %for.cond18.preheader
+
+for.cond.cleanup20: ; preds = %for.body21, %for.cond18.preheader
+ %add27 = add i64 %1, %n.071
+ %cmp4 = icmp ult i64 %add27, %ATN
+ br i1 %cmp4, label %for.body6, label %for.cond.cleanup5
+
+for.body21: ; preds = %for.cond18.preheader, %for.body21
+ %i.069 = phi i64 [ %inc, %for.body21 ], [ 0, %for.cond18.preheader ]
+ %c00.067 = phi ptr [ %add.ptr24, %for.body21 ], [ %add.ptr10, %for.cond18.preheader ]
+ tail call void @llvm.riscv.sf.vste32.i64(i64 %i.069, ptr %c00.067, i64 %1)
+ %inc = add nuw i64 %i.069, 1
+ %add.ptr24 = getelementptr inbounds nuw float, ptr %c00.067, i64 %ldc
+ %exitcond.not = icmp eq i64 %inc, %0
+ br i1 %exitcond.not, label %for.cond.cleanup20, label %for.body21
+
+return: ; preds = %entry, %for.cond.cleanup
+ ret void
+}
+
+declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1
+declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1
+declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #2
+declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1
+declare <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.i64(<vscale x 16 x half>, ptr captures(none), i64) #3
+declare <vscale x 32 x half> @llvm.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half>, <vscale x 16 x half>, i64 immarg) #4
+declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64 immarg) #2
+declare <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.i64(<vscale x 32 x half>, ptr captures(none), i64) #3
+declare <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #2
+declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half>, <vscale x 16 x float>, i64 immarg, i64) #1
+declare void @llvm.riscv.vse.nxv16f16.i64(<vscale x 16 x half>, ptr captures(none), i64) #5
+declare void @llvm.riscv.sf.vtdiscard() #2
+declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float>, ptr captures(none), i64) #3
+declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, <vscale x 16 x float>, <vscale x 16 x float>, i64, i64, i64, i64 immarg) #2
+declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #4
>From 5b484c5e33f0c47457c16a22d71474d86ffd141b Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 11 Jun 2026 19:27:28 -0700
Subject: [PATCH 2/8] [RISCV] coalesce between VSETVLI and SF_VSETTNT
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 98 +++++++++++++++++++
.../CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll | 10 +-
2 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index f964979baa412..c51524fae4bfa 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -141,6 +141,9 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
const DemandedFields &Used,
MachineInstr *&AVLDefToMove) const;
void coalesceVSETVLIs(MachineBasicBlock &MBB) const;
+ bool canMutatePriorConfigWithTWiden(const MachineInstr &PrevMI,
+ const MachineInstr &MI) const;
+ void coalesceVSETVLIsForTWiden(MachineBasicBlock &MBB) const;
bool insertVSETMTK(MachineBasicBlock &MBB, TKTMMode Mode) const;
};
@@ -933,6 +936,98 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
}
}
+// When twiden != 0, LMUL, tail policy, and mask policy from the user are
+// ignored. The tail policy and mask policy are always treated as agnostic. The
+// normal RVV instruction will ignore the twiden parameter. This observation
+// could allow the RVV instruction and xsfmm instruction to share the same
+// configuration instruction.
+//
+// We need to make sure the AVL, SEW, and AltFmt is same between VSETVL and
+// VSETVLTN.
+//
+// For example:
+//
+// %avl = SETTM or SETTK
+// ...
+// VSETVL %avl, type1
+// VSETVLTNT %avl, type2
+//
+// ->
+//
+// %avl = SETTM or SETTK
+// ...
+// VSETVLTNT %avl, type2
+//
+bool RISCVInsertVSETVLI::canMutatePriorConfigWithTWiden(
+ const MachineInstr &PrevMI, const MachineInstr &MI) const {
+
+ if (PrevMI.getOpcode() != RISCV::PseudoVSETVLI)
+ return false;
+
+ if (MI.getOpcode() != RISCV::PseudoSF_VSETTNT)
+ return false;
+
+ auto PrevInfo = VIA.getInfoForVSETVLI(PrevMI);
+ auto CurrInfo = VIA.getInfoForVSETVLI(MI);
+
+ auto AVLReg = CurrInfo.getAVLReg();
+
+ auto *AVLRegDefMI = MRI->getUniqueVRegDef(AVLReg);
+
+ if (!AVLRegDefMI)
+ return false;
+
+ if (!RISCVInstrInfo::isXSfmmVectorConfigTMTKInstr(*AVLRegDefMI))
+ return false;
+
+ auto AVLRegDefMIInfo = VIA.computeInfoForInstr(*AVLRegDefMI);
+ if (AVLRegDefMIInfo.getTWiden() != CurrInfo.getTWiden())
+ return false;
+
+ if (AVLRegDefMIInfo.getSEW() != PrevInfo.getSEW())
+ return false;
+
+ // CurrInfo twiden != 0, so TailAgnostic and MaskAgnostic bit default to 1
+ if (!PrevInfo.getTailAgnostic() || !PrevInfo.getMaskAgnostic())
+ return false;
+
+ if (!PrevInfo.hasSameAVL(CurrInfo))
+ return false;
+
+ if (PrevInfo.getSEW() != CurrInfo.getSEW())
+ return false;
+
+ if (PrevInfo.getAltFmt() != CurrInfo.getAltFmt())
+ return false;
+
+ return true;
+}
+
+void RISCVInsertVSETVLI::coalesceVSETVLIsForTWiden(
+ MachineBasicBlock &MBB) const {
+ MachineInstr *NextMI = nullptr;
+
+ for (MachineInstr &MI : make_early_inc_range(reverse(MBB))) {
+
+ if (!RISCVInstrInfo::isVectorConfigInstr(MI))
+ continue;
+
+ if (NextMI) {
+ // If only TWiden different. Update the MI and drop the NextMI.
+ if (canMutatePriorConfigWithTWiden(MI, *NextMI)) {
+
+ auto NextInfo = VIA.getInfoForVSETVLI(*NextMI);
+ MI.getOperand(2).setImm(NextInfo.encodeVTYPE());
+
+ if (LIS)
+ LIS->RemoveMachineInstrFromMaps(*NextMI);
+ NextMI->eraseFromParent();
+ }
+ }
+ NextMI = &MI;
+ }
+}
+
void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
MachineInstr &MI = *I++;
@@ -1089,6 +1184,9 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock *MBB : post_order(&MF))
coalesceVSETVLIs(*MBB);
+ for (MachineBasicBlock &MBB : MF)
+ coalesceVSETVLIsForTWiden(MBB);
+
// Insert PseudoReadVL after VLEFF/VLSEGFF and replace it with the vl output
// of VLEFF/VLSEGFF.
for (MachineBasicBlock &MBB : MF)
diff --git a/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll b/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
index 5278d57fc41d0..2db0809c2fcf9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
@@ -246,9 +246,8 @@ define void @matmulf16(i64 noundef %ATM, i64 noundef %ATN, i64 noundef %ATK, ptr
; X280-NEXT: beqz a2, .LBB0_10
; X280-NEXT: # %bb.9: # %if.then18
; X280-NEXT: # in Loop: Header=BB0_6 Depth=2
-; X280-NEXT: vsetvli zero, s2, e16, m8, ta, ma
-; X280-NEXT: vle16.v v8, (s6)
; X280-NEXT: sf.vsettnt zero, s2, e16, w2
+; X280-NEXT: vle16.v v8, (s6)
; X280-NEXT: sf.vsettk s6, t6
; X280-NEXT: vsetvli zero, s4, e16, m8, ta, ma
; X280-NEXT: sub a2, t6, s6
@@ -576,13 +575,12 @@ define void @matmul32(i64 noundef %ATM, i64 noundef %ATN, i64 noundef %ATK, ptr
; X280-NEXT: # Parent Loop BB1_4 Depth=1
; X280-NEXT: # Parent Loop BB1_6 Depth=2
; X280-NEXT: # => This Inner Loop Header: Depth=3
-; X280-NEXT: vsetvli zero, t5, e32, m8, ta, ma
-; X280-NEXT: vle32.v v8, (s3)
-; X280-NEXT: sub s4, a2, s1
-; X280-NEXT: add s3, s3, a4
; X280-NEXT: sf.vsettnt zero, t5, e32, w1
+; X280-NEXT: sub s4, a2, s1
+; X280-NEXT: vle32.v v8, (s3)
; X280-NEXT: sf.vsettk s4, s4
; X280-NEXT: vsetvli zero, s0, e32, m8, ta, ma
+; X280-NEXT: add s3, s3, a4
; X280-NEXT: add s1, s1, s4
; X280-NEXT: vle32.v v16, (s2)
; X280-NEXT: add s2, s2, a6
>From f6195e54bc27317f317855764d84548b695689a2 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 16 Jun 2026 22:29:28 -0700
Subject: [PATCH 3/8] !fixup guard with hasVendorXSfmmbase
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index c51524fae4bfa..00527e16695cc 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1184,8 +1184,10 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock *MBB : post_order(&MF))
coalesceVSETVLIs(*MBB);
- for (MachineBasicBlock &MBB : MF)
- coalesceVSETVLIsForTWiden(MBB);
+ if (ST->hasVendorXSfmmbase()) {
+ for (MachineBasicBlock &MBB : MF)
+ coalesceVSETVLIsForTWiden(MBB);
+ }
// Insert PseudoReadVL after VLEFF/VLSEGFF and replace it with the vl output
// of VLEFF/VLSEGFF.
>From cf186d4faa3c77a8387ba9ca0306c9c8b5521329 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 16 Jun 2026 23:19:55 -0700
Subject: [PATCH 4/8] !fixup consider the PrevMI's LMUL and KMAX of Twiden
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 00527e16695cc..a627b05b36f52 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1000,6 +1000,17 @@ bool RISCVInsertVSETVLI::canMutatePriorConfigWithTWiden(
if (PrevInfo.getAltFmt() != CurrInfo.getAltFmt())
return false;
+ // The PrevMI's LMUL should be at least 8/KMAX; otherwise, converting it to a
+ // tail-widening version would result in a VLMAX smaller than what AVLRegDefMI
+ // expects, causing the LMUL information from PrevMI to be lost.
+ unsigned LMul;
+ bool Fractional;
+ std::tie(LMul, Fractional) = decodeVLMUL(PrevInfo.getVLMUL());
+ unsigned KMAX = (CurrInfo.getSEW() >= 32) ? 1 : (32 / CurrInfo.getSEW());
+
+ if (Fractional || LMul < (8 / KMAX))
+ return false;
+
return true;
}
>From bb31eab77745ff6dbb0680e46648a4421baab822 Mon Sep 17 00:00:00 2001
From: Piyou Chen <gccbg04538 at gmail.com>
Date: Wed, 1 Jul 2026 14:41:40 +0800
Subject: [PATCH 5/8] Update llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Co-authored-by: Luke Lau <luke_lau at icloud.com>
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index a627b05b36f52..38fa7f8ec6639 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1003,9 +1003,7 @@ bool RISCVInsertVSETVLI::canMutatePriorConfigWithTWiden(
// The PrevMI's LMUL should be at least 8/KMAX; otherwise, converting it to a
// tail-widening version would result in a VLMAX smaller than what AVLRegDefMI
// expects, causing the LMUL information from PrevMI to be lost.
- unsigned LMul;
- bool Fractional;
- std::tie(LMul, Fractional) = decodeVLMUL(PrevInfo.getVLMUL());
+ auto [LMul, Fractional] = decodeVLMUL(PrevInfo.getVLMUL());
unsigned KMAX = (CurrInfo.getSEW() >= 32) ? 1 : (32 / CurrInfo.getSEW());
if (Fractional || LMul < (8 / KMAX))
>From faa07626c1a503deea0108cc8ee224ea3d493b7e Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 1 Jul 2026 00:43:59 -0700
Subject: [PATCH 6/8] !fixup Add assert for check sf.vsettnt has AVL
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 38fa7f8ec6639..c689d2c4f5e05 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -970,6 +970,8 @@ bool RISCVInsertVSETVLI::canMutatePriorConfigWithTWiden(
auto PrevInfo = VIA.getInfoForVSETVLI(PrevMI);
auto CurrInfo = VIA.getInfoForVSETVLI(MI);
+ assert(CurrInfo.hasAVLReg() && "Invalid PseudoSF_VSETTNT without an AVLReg.");
+
auto AVLReg = CurrInfo.getAVLReg();
auto *AVLRegDefMI = MRI->getUniqueVRegDef(AVLReg);
>From a013147531c225504915e5ea435f347266eb4acc Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 15 Jul 2026 21:09:59 -0700
Subject: [PATCH 7/8] !fixup refine comment
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index c689d2c4f5e05..b7f8022adfdc1 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1003,7 +1003,7 @@ bool RISCVInsertVSETVLI::canMutatePriorConfigWithTWiden(
return false;
// The PrevMI's LMUL should be at least 8/KMAX; otherwise, converting it to a
- // tail-widening version would result in a VLMAX smaller than what AVLRegDefMI
+ // tile-widening version could result in a VLMAX smaller than what AVLRegDefMI
// expects, causing the LMUL information from PrevMI to be lost.
auto [LMul, Fractional] = decodeVLMUL(PrevInfo.getVLMUL());
unsigned KMAX = (CurrInfo.getSEW() >= 32) ? 1 : (32 / CurrInfo.getSEW());
>From bade190657908be3d6585cb789ba7a0f8cace2db Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 15 Jul 2026 21:13:56 -0700
Subject: [PATCH 8/8] !fixup update testcase
---
.../CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll | 337 ++++++++----------
1 file changed, 147 insertions(+), 190 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll b/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
index 2db0809c2fcf9..377478b165567 100644
--- a/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/xsfmm-vsetvl-removal.ll
@@ -1,161 +1,140 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+xsfmmbase,+xsfmm32a,+xsfmm32a8f,+xsfmm64a64f | FileCheck %s
-; RUN: llc < %s -mcpu=sifive-x280 -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+xsfmmbase,+xsfmm32a,+xsfmm32a8f,+xsfmm64a64f | FileCheck %s -check-prefix=X280
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin,+xsfmmbase,+xsfmm32a,+xsfmm32a8f,+xsfmm64a64f | FileCheck %s
+; RUN: llc < %s -mcpu=sifive-x280 -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin,+xsfmmbase,+xsfmm32a,+xsfmm32a8f,+xsfmm64a64f | FileCheck %s -check-prefix=X280
define void @matmulf16(i64 noundef %ATM, i64 noundef %ATN, i64 noundef %ATK, ptr noundef readonly captures(none) %a, i64 noundef %lda, ptr noundef readonly captures(none) %b, i64 noundef %ldb, ptr noundef writeonly captures(none) %c, i64 noundef %ldc) nounwind {
; CHECK-LABEL: matmulf16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -144
-; CHECK-NEXT: sd ra, 136(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 128(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s1, 120(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s2, 112(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s3, 104(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s4, 96(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s5, 88(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s6, 80(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s7, 72(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s8, 64(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s9, 56(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s10, 48(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s11, 40(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd a7, 24(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd a3, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: beqz a0, .LBB0_14
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: mv s4, a1
; CHECK-NEXT: beqz a1, .LBB0_14
; CHECK-NEXT: # %bb.2: # %for.body6.lr.ph.preheader
-; CHECK-NEXT: mv s1, a5
-; CHECK-NEXT: mv s7, a2
-; CHECK-NEXT: li a2, 0
-; CHECK-NEXT: ld s6, 144(sp)
-; CHECK-NEXT: slli s8, a4, 2
-; CHECK-NEXT: slli s9, a4, 1
-; CHECK-NEXT: slli s10, a6, 2
-; CHECK-NEXT: slli s11, a6, 1
-; CHECK-NEXT: slli s6, s6, 1
-; CHECK-NEXT: li s0, 2
-; CHECK-NEXT: li s3, 1
-; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi sp, sp, -80
+; CHECK-NEXT: sd s0, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s1, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s2, 56(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s3, 48(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s4, 40(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s5, 32(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s6, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s7, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s8, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: li t0, 0
+; CHECK-NEXT: ld t1, 80(sp)
+; CHECK-NEXT: slli t2, a4, 2
+; CHECK-NEXT: slli a4, a4, 1
+; CHECK-NEXT: slli t3, a6, 2
+; CHECK-NEXT: slli a6, a6, 1
+; CHECK-NEXT: slli t4, t1, 1
+; CHECK-NEXT: li t5, 2
+; CHECK-NEXT: li t6, 1
; CHECK-NEXT: j .LBB0_4
; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup5
; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=1
-; CHECK-NEXT: ld a2, 32(sp) # 8-byte Folded Reload
-; CHECK-NEXT: add a2, s5, a2
-; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: bgeu a2, a0, .LBB0_13
+; CHECK-NEXT: add t0, s1, t0
+; CHECK-NEXT: bgeu t0, a0, .LBB0_13
; CHECK-NEXT: .LBB0_4: # %for.body6.lr.ph
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB0_6 Depth 2
; CHECK-NEXT: # Child Loop BB0_7 Depth 3
; CHECK-NEXT: # Child Loop BB0_12 Depth 3
-; CHECK-NEXT: sub a0, a0, a2
-; CHECK-NEXT: slli s2, a2, 1
-; CHECK-NEXT: sf.vsettnt a1, zero, e16, w2
-; CHECK-NEXT: sf.vsettm s5, a0
-; CHECK-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
-; CHECK-NEXT: add s2, a0, s2
-; CHECK-NEXT: sd a2, 32(sp) # 8-byte Folded Spill
-; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: ld a1, 144(sp)
-; CHECK-NEXT: call __muldi3
-; CHECK-NEXT: li a1, 0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: ld a2, 24(sp) # 8-byte Folded Reload
-; CHECK-NEXT: add a0, a2, a0
+; CHECK-NEXT: li s0, 0
+; CHECK-NEXT: mul s2, t0, t1
+; CHECK-NEXT: sub s1, a0, t0
+; CHECK-NEXT: sf.vsettnt s3, zero, e16, w2
+; CHECK-NEXT: sf.vsettm s1, s1
+; CHECK-NEXT: slli s3, t0, 1
+; CHECK-NEXT: slli s4, s2, 1
+; CHECK-NEXT: add s2, a3, s3
+; CHECK-NEXT: add s3, a7, s4
; CHECK-NEXT: j .LBB0_6
; CHECK-NEXT: .LBB0_5: # %for.cond.cleanup28
; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: bgeu a1, s4, .LBB0_3
+; CHECK-NEXT: add s0, s4, s0
+; CHECK-NEXT: bgeu s0, a1, .LBB0_3
; CHECK-NEXT: .LBB0_6: # %for.body6
; CHECK-NEXT: # Parent Loop BB0_4 Depth=1
; CHECK-NEXT: # => This Loop Header: Depth=2
; CHECK-NEXT: # Child Loop BB0_7 Depth 3
; CHECK-NEXT: # Child Loop BB0_12 Depth 3
-; CHECK-NEXT: sub a2, s4, a1
-; CHECK-NEXT: sf.vsettnt a2, a2, e16, w2
-; CHECK-NEXT: slli a3, a1, 1
+; CHECK-NEXT: sub s4, a1, s0
+; CHECK-NEXT: sf.vsettnt s4, s4, e16, w2
+; CHECK-NEXT: slli s5, s0, 1
; CHECK-NEXT: sf.vsettnt zero, zero, e16, w2
-; CHECK-NEXT: sf.vsettm zero, s5
+; CHECK-NEXT: sf.vsettm zero, s1
; CHECK-NEXT: sf.vtzero.t mt0
-; CHECK-NEXT: add a4, s1, a3
-; CHECK-NEXT: mv a5, s2
-; CHECK-NEXT: bltu s7, s0, .LBB0_8
+; CHECK-NEXT: add s6, a5, s5
+; CHECK-NEXT: mv s7, s2
+; CHECK-NEXT: bltu a2, t5, .LBB0_8
; CHECK-NEXT: .LBB0_7: # %while.body
; CHECK-NEXT: # Parent Loop BB0_4 Depth=1
; CHECK-NEXT: # Parent Loop BB0_6 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
-; CHECK-NEXT: vsetvli zero, s5, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: add a6, a5, s9
-; CHECK-NEXT: vle16.v v12, (a6)
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v16, (a4)
-; CHECK-NEXT: add a6, a4, s11
-; CHECK-NEXT: vle16.v v20, (a6)
-; CHECK-NEXT: sf.vsettnt zero, a2, e16, w2
-; CHECK-NEXT: sf.vsettk a6, s7
-; CHECK-NEXT: sf.vsettm zero, s5
-; CHECK-NEXT: sf.vsettk zero, a6
+; CHECK-NEXT: vsetvli zero, s1, e16, m4, ta, ma
+; CHECK-NEXT: vle16.v v8, (s7)
+; CHECK-NEXT: add s8, s7, a4
+; CHECK-NEXT: vle16.v v12, (s8)
+; CHECK-NEXT: vsetvli zero, s4, e16, m4, ta, ma
+; CHECK-NEXT: vle16.v v16, (s6)
+; CHECK-NEXT: add s8, s6, a6
+; CHECK-NEXT: vle16.v v20, (s8)
+; CHECK-NEXT: sf.vsettnt zero, s4, e16, w2
+; CHECK-NEXT: sf.vsettk s8, a2
+; CHECK-NEXT: sf.vsettm zero, s1
+; CHECK-NEXT: sf.vsettk zero, s8
; CHECK-NEXT: sf.mm.f.f mt0, v8, v16
-; CHECK-NEXT: sub s7, s7, a6
-; CHECK-NEXT: add a5, a5, s8
-; CHECK-NEXT: add a4, a4, s10
-; CHECK-NEXT: bltu s3, s7, .LBB0_7
+; CHECK-NEXT: sub a2, a2, s8
+; CHECK-NEXT: add s7, s7, t2
+; CHECK-NEXT: add s6, s6, t3
+; CHECK-NEXT: bltu t6, a2, .LBB0_7
; CHECK-NEXT: .LBB0_8: # %while.end
; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
-; CHECK-NEXT: beqz s7, .LBB0_10
+; CHECK-NEXT: beqz a2, .LBB0_10
; CHECK-NEXT: # %bb.9: # %if.then18
; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
-; CHECK-NEXT: vsetvli zero, s5, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v16, (a4)
-; CHECK-NEXT: sf.vsettnt zero, a2, e16, w2
-; CHECK-NEXT: sf.vsettk a4, s3
-; CHECK-NEXT: sf.vsettm zero, s5
-; CHECK-NEXT: sf.vsettk zero, a4
+; CHECK-NEXT: vsetvli zero, s1, e16, m8, ta, ma
+; CHECK-NEXT: vle16.v v8, (s7)
+; CHECK-NEXT: vsetvli zero, s4, e16, m8, ta, ma
+; CHECK-NEXT: vle16.v v16, (s6)
+; CHECK-NEXT: sf.vsettnt zero, s4, e16, w2
+; CHECK-NEXT: sf.vsettk a2, t6
+; CHECK-NEXT: sf.vsettm zero, s1
+; CHECK-NEXT: sf.vsettk zero, a2
; CHECK-NEXT: sf.mm.f.f mt0, v8, v16
-; CHECK-NEXT: sub s7, s3, a4
+; CHECK-NEXT: sub a2, t6, a2
; CHECK-NEXT: .LBB0_10: # %if.end25
; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
-; CHECK-NEXT: beqz s5, .LBB0_5
+; CHECK-NEXT: beqz s1, .LBB0_5
; CHECK-NEXT: # %bb.11: # %for.body29.preheader
; CHECK-NEXT: # in Loop: Header=BB0_6 Depth=2
-; CHECK-NEXT: li a4, 0
-; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: li s6, 0
+; CHECK-NEXT: add s5, s3, s5
; CHECK-NEXT: .LBB0_12: # %for.body29
; CHECK-NEXT: # Parent Loop BB0_4 Depth=1
; CHECK-NEXT: # Parent Loop BB0_6 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
-; CHECK-NEXT: sf.vsettnt zero, a2, e32, w1
-; CHECK-NEXT: sf.vtmv.v.t v8, a4
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: sf.vsettnt zero, s4, e32, w1
+; CHECK-NEXT: sf.vtmv.v.t v8, s6
+; CHECK-NEXT: vsetvli zero, s4, e16, m4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v16, v8
-; CHECK-NEXT: addi a4, a4, 1
-; CHECK-NEXT: vse16.v v16, (a3)
-; CHECK-NEXT: add a3, a3, s6
-; CHECK-NEXT: bne s5, a4, .LBB0_12
+; CHECK-NEXT: addi s6, s6, 1
+; CHECK-NEXT: vse16.v v16, (s5)
+; CHECK-NEXT: add s5, s5, t4
+; CHECK-NEXT: bne s1, s6, .LBB0_12
; CHECK-NEXT: j .LBB0_5
; CHECK-NEXT: .LBB0_13: # %for.cond.cleanup
; CHECK-NEXT: sf.vtdiscard
+; CHECK-NEXT: ld s0, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s1, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s2, 56(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s3, 48(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s4, 40(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s5, 32(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s6, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s7, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s8, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 80
; CHECK-NEXT: .LBB0_14: # %return
-; CHECK-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s1, 120(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s2, 112(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s3, 104(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s4, 96(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s5, 88(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s6, 80(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s7, 72(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s8, 64(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s9, 56(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s10, 48(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s11, 40(sp) # 8-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 144
; CHECK-NEXT: ret
;
; X280-LABEL: matmulf16:
@@ -391,129 +370,107 @@ return: ; preds = %entry, %for.cond.cl
define void @matmul32(i64 noundef %ATM, i64 noundef %ATN, i64 noundef %ATK, ptr noundef readonly captures(none) %a, i64 noundef %lda, ptr noundef readonly captures(none) %b, i64 noundef %ldb, ptr noundef writeonly captures(none) %c, i64 noundef %ldc) nounwind {
; CHECK-LABEL: matmul32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -112
-; CHECK-NEXT: sd ra, 104(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s0, 96(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s1, 88(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s2, 80(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s3, 72(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s4, 64(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s5, 56(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s6, 48(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s7, 40(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s8, 32(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s9, 24(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s10, 16(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: beqz a0, .LBB1_13
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: mv s5, a1
; CHECK-NEXT: beqz a1, .LBB1_13
; CHECK-NEXT: # %bb.2: # %for.cond.preheader
-; CHECK-NEXT: mv s0, a7
-; CHECK-NEXT: mv s1, a5
-; CHECK-NEXT: mv s2, a0
-; CHECK-NEXT: mv s7, a3
-; CHECK-NEXT: mv s4, a2
-; CHECK-NEXT: li s6, 0
-; CHECK-NEXT: ld s10, 112(sp)
-; CHECK-NEXT: slli s8, a6, 2
-; CHECK-NEXT: slli s9, a4, 2
-; CHECK-NEXT: slli s10, s10, 2
+; CHECK-NEXT: addi sp, sp, -48
+; CHECK-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s1, 32(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s2, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s3, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s5, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT: li t0, 0
+; CHECK-NEXT: ld t1, 48(sp)
+; CHECK-NEXT: slli a6, a6, 2
+; CHECK-NEXT: slli a4, a4, 2
+; CHECK-NEXT: slli t2, t1, 2
; CHECK-NEXT: j .LBB1_4
; CHECK-NEXT: .LBB1_3: # %for.cond.cleanup5
; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1
-; CHECK-NEXT: add s6, s11, s6
-; CHECK-NEXT: bgeu s6, s2, .LBB1_12
+; CHECK-NEXT: add t0, t4, t0
+; CHECK-NEXT: bgeu t0, a0, .LBB1_12
; CHECK-NEXT: .LBB1_4: # %for.body6.lr.ph
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB1_6 Depth 2
; CHECK-NEXT: # Child Loop BB1_8 Depth 3
; CHECK-NEXT: # Child Loop BB1_11 Depth 3
-; CHECK-NEXT: sub a0, s2, s6
-; CHECK-NEXT: slli s3, s6, 2
-; CHECK-NEXT: sf.vsettnt a1, zero, e32, w1
-; CHECK-NEXT: sf.vsettm s11, a0
-; CHECK-NEXT: add s3, s7, s3
-; CHECK-NEXT: mv a0, s6
-; CHECK-NEXT: ld a1, 112(sp)
-; CHECK-NEXT: call __muldi3
-; CHECK-NEXT: li a1, 0
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add a0, s0, a0
+; CHECK-NEXT: li t3, 0
+; CHECK-NEXT: mul t5, t0, t1
+; CHECK-NEXT: sub t4, a0, t0
+; CHECK-NEXT: sf.vsettnt t6, zero, e32, w1
+; CHECK-NEXT: sf.vsettm t4, t4
+; CHECK-NEXT: slli t6, t0, 2
+; CHECK-NEXT: slli s0, t5, 2
+; CHECK-NEXT: add t5, a3, t6
+; CHECK-NEXT: add t6, a7, s0
; CHECK-NEXT: j .LBB1_6
; CHECK-NEXT: .LBB1_5: # %for.cond.cleanup20
; CHECK-NEXT: # in Loop: Header=BB1_6 Depth=2
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: bgeu a1, s5, .LBB1_3
+; CHECK-NEXT: add t3, s0, t3
+; CHECK-NEXT: bgeu t3, a1, .LBB1_3
; CHECK-NEXT: .LBB1_6: # %for.body6
; CHECK-NEXT: # Parent Loop BB1_4 Depth=1
; CHECK-NEXT: # => This Loop Header: Depth=2
; CHECK-NEXT: # Child Loop BB1_8 Depth 3
; CHECK-NEXT: # Child Loop BB1_11 Depth 3
-; CHECK-NEXT: sub a2, s5, a1
-; CHECK-NEXT: sf.vsettnt a2, a2, e32, w1
+; CHECK-NEXT: sub s0, a1, t3
+; CHECK-NEXT: sf.vsettnt s0, s0, e32, w1
; CHECK-NEXT: sf.vsettnt zero, zero, e32, w1
-; CHECK-NEXT: sf.vsettm zero, s11
+; CHECK-NEXT: sf.vsettm zero, t4
; CHECK-NEXT: sf.vtzero.t mt0
-; CHECK-NEXT: slli a3, a1, 2
-; CHECK-NEXT: beqz s4, .LBB1_9
+; CHECK-NEXT: slli s1, t3, 2
+; CHECK-NEXT: beqz a2, .LBB1_9
; CHECK-NEXT: # %bb.7: # %for.body14.preheader
; CHECK-NEXT: # in Loop: Header=BB1_6 Depth=2
-; CHECK-NEXT: li a4, 0
-; CHECK-NEXT: add a5, s1, a3
-; CHECK-NEXT: mv a6, s3
+; CHECK-NEXT: li s2, 0
+; CHECK-NEXT: add s3, a5, s1
+; CHECK-NEXT: mv s4, t5
; CHECK-NEXT: .LBB1_8: # %for.body14
; CHECK-NEXT: # Parent Loop BB1_4 Depth=1
; CHECK-NEXT: # Parent Loop BB1_6 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
-; CHECK-NEXT: vsetvli zero, s11, e32, m8, ta, ma
-; CHECK-NEXT: vle32.v v8, (a6)
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vle32.v v16, (a5)
-; CHECK-NEXT: sub a7, s4, a4
-; CHECK-NEXT: sf.vsettnt zero, a2, e32, w1
-; CHECK-NEXT: sf.vsettk a7, a7
-; CHECK-NEXT: sf.vsettm zero, s11
-; CHECK-NEXT: sf.vsettk zero, a7
+; CHECK-NEXT: vsetvli zero, t4, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v8, (s4)
+; CHECK-NEXT: vsetvli zero, s0, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v16, (s3)
+; CHECK-NEXT: sub s5, a2, s2
+; CHECK-NEXT: sf.vsettnt zero, s0, e32, w1
+; CHECK-NEXT: sf.vsettk s5, s5
+; CHECK-NEXT: sf.vsettm zero, t4
+; CHECK-NEXT: sf.vsettk zero, s5
; CHECK-NEXT: sf.mm.f.f mt0, v8, v16
-; CHECK-NEXT: add a4, a7, a4
-; CHECK-NEXT: add a5, a5, s8
-; CHECK-NEXT: add a6, a6, s9
-; CHECK-NEXT: bltu a4, s4, .LBB1_8
+; CHECK-NEXT: add s2, s5, s2
+; CHECK-NEXT: add s3, s3, a6
+; CHECK-NEXT: add s4, s4, a4
+; CHECK-NEXT: bltu s2, a2, .LBB1_8
; CHECK-NEXT: .LBB1_9: # %for.cond18.preheader
; CHECK-NEXT: # in Loop: Header=BB1_6 Depth=2
-; CHECK-NEXT: beqz s11, .LBB1_5
+; CHECK-NEXT: beqz t4, .LBB1_5
; CHECK-NEXT: # %bb.10: # %for.body21.preheader
; CHECK-NEXT: # in Loop: Header=BB1_6 Depth=2
-; CHECK-NEXT: li a4, 0
-; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: li s2, 0
+; CHECK-NEXT: add s1, t6, s1
; CHECK-NEXT: .LBB1_11: # %for.body21
; CHECK-NEXT: # Parent Loop BB1_4 Depth=1
; CHECK-NEXT: # Parent Loop BB1_6 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
-; CHECK-NEXT: sf.vste32 a4, (a3)
-; CHECK-NEXT: addi a4, a4, 1
-; CHECK-NEXT: add a3, a3, s10
-; CHECK-NEXT: bne s11, a4, .LBB1_11
+; CHECK-NEXT: sf.vste32 s2, (s1)
+; CHECK-NEXT: addi s2, s2, 1
+; CHECK-NEXT: add s1, s1, t2
+; CHECK-NEXT: bne t4, s2, .LBB1_11
; CHECK-NEXT: j .LBB1_5
; CHECK-NEXT: .LBB1_12: # %for.cond.cleanup
; CHECK-NEXT: sf.vtdiscard
+; CHECK-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s1, 32(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s2, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s3, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s5, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 48
; CHECK-NEXT: .LBB1_13: # %return
-; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s1, 88(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s2, 80(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s3, 72(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s4, 64(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s5, 56(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s6, 48(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s7, 40(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s8, 32(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s9, 24(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s10, 16(sp) # 8-byte Folded Reload
-; CHECK-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: addi sp, sp, 112
; CHECK-NEXT: ret
;
; X280-LABEL: matmul32:
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