[llvm] [PassBuilder] Add extra ModuleInliner/SROA/SimplifyCFG/LICM to late FullLTO passes (PR #197678)

[Luke Lau via llvm-commits]

https://github.com/lukel97 commented:

RISC-V results on SPEC CPU 2017 look good https://lnt.lukelau.me/db_default/v4/nts/1631?compare_to=1630

https://github.com/llvm/llvm-project/pull/197678