[llvm] [AMDGPU][True16] Fix MadMix selection (PR #205431)
Domenic Nutile via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 15 07:47:45 PDT 2026
https://github.com/saxlungs updated https://github.com/llvm/llvm-project/pull/205431
>From f835f4aaa4f4c5113730b49ff8264764984f5e13 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Tue, 23 Jun 2026 16:55:52 -0400
Subject: [PATCH 1/2] [AMDGPU][True16] Fix MadMix selection
The mad-mix instruction selection combines fpext on src operands into the mad-mix itself. This makes the truncate flowing into fpext useless and result in incorrect register classes.
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 7 +
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll | 114 +++-
llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll | 447 +++++++++----
llvm/test/CodeGen/AMDGPU/mad-mix.ll | 617 +++++++++++++-----
4 files changed, 858 insertions(+), 327 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 9d44d4c5424a3..9547b07728ce5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -7225,6 +7225,13 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
Mods |= SISrcMods::OP_SEL_0;
CheckAbsNeg();
}
+ // Since we looked through FPEXT and removed it, we must also remove
+ // G_TRUNC. G_TRUNC to 16-bits would have a destination in RC VGPR_16, which
+ // is not compatible with MadMix instructions
+ Register PeekSrc = Src;
+ if (Subtarget->useRealTrue16Insts() &&
+ mi_match(PeekSrc, *MRI, m_GTrunc(m_Reg(PeekSrc))))
+ Src = PeekSrc;
Matched = true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index 1c24a2c8e3798..fa9854a2f4ea3 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -5,8 +5,7 @@
; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,SDAG-VI %s
; RUN: llc -mtriple=amdgpu7.01 < %s | FileCheck -check-prefixes=SDAG-CI %s
-; FIXME-TRUE16. fix gisel
-; XUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,GISEL-VI %s
@@ -114,14 +113,21 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo(half %src0, half %s
; SDAG-CI-NEXT: v_or_b32_e32 v0, 0x3c00, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v3, 0x3c00
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
+; GISEL-GFX11-TRUE16: ; %bb.0:
+; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3c00
+; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
+; GISEL-GFX11-FAKE16: ; %bb.0:
+; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GISEL-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:
; GISEL-CI: ; %bb.0:
@@ -221,13 +227,13 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo(half %src0, half %src
}
define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, half %src2) #0 {
-; GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
; GFX9: ; %bb.0:
@@ -257,6 +263,23 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, ha
; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
+; GISEL-GFX11-TRUE16: ; %bb.0:
+; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
+; GISEL-GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
+; GISEL-GFX11-FAKE16: ; %bb.0:
+; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -279,13 +302,13 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, ha
}
define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src1, half %src2) #0 {
-; GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
+; SDAG-GFX11: ; %bb.0:
+; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX11-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
; GFX9: ; %bb.0:
@@ -315,6 +338,23 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src
; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
+; GISEL-GFX11-TRUE16: ; %bb.0:
+; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GISEL-GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
+; GISEL-GFX11-FAKE16: ; %bb.0:
+; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -382,14 +422,22 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
+; GISEL-GFX11-TRUE16: ; %bb.0:
+; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v0
+; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
+; GISEL-GFX11-FAKE16: ; %bb.0:
+; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
; GISEL-CI: ; %bb.0:
@@ -597,9 +645,7 @@ declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #
attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL-GFX11-FAKE16: {{.*}}
; GISEL-GFX9: {{.*}}
; GISEL-VI: {{.*}}
-; SDAG-GFX11: {{.*}}
; SDAG-GFX9: {{.*}}
; SDAG-VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
index d5514894cb2dc..7392137287d97 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
@@ -6,8 +6,7 @@
; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,SDAG-VI %s
; RUN: llc -mtriple=amdgpu7.01 < %s | FileCheck -check-prefixes=SDAG-CI %s
-; FIXME-TRUE16. enable gisel
-; XUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.06 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
@@ -388,13 +387,21 @@ define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt(half %src0, half %src
; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt:
; GISEL-CI: ; %bb.0:
@@ -487,14 +494,26 @@ define <2 x half> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half
; SDAG-CI-NEXT: v_or_b32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v3, v4, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mix_v2f32:
; GISEL-CI: ; %bb.0:
@@ -608,17 +627,32 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
; SDAG-CI-NEXT: v_or_b32_e32 v0, v2, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v3f32:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v3f32:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v6, v7, v8 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v9, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32:
; GISEL-GFX900: ; %bb.0:
@@ -782,17 +816,36 @@ define <4 x half> @v_mad_mix_v4f32(<4 x half> %src0, <4 x half> %src1, <4 x half
; SDAG-CI-NEXT: v_or_b32_e32 v1, v3, v4
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v4f32:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v4f32:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v6, v8, v9 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v2, v7, v10, v11 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v6
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v4f32:
; GISEL-GFX900: ; %bb.0:
@@ -943,14 +996,25 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %s
; SDAG-CI-NEXT: v_or_b32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_clamp_postcvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_postcvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v3, v4, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_postcvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mix_v2f32_clamp_postcvt:
; GISEL-CI: ; %bb.0:
@@ -1111,18 +1175,31 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
; SDAG-CI-NEXT: v_or_b32_e32 v0, v0, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v3f32_clamp_postcvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GISEL-GFX1100-NEXT: v_pk_max_f16 v1, v1, v1 clamp
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v3f32_clamp_postcvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v6, v7, v8 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32_clamp_postcvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_and_b32 v1, 0xffff, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GISEL-GFX1100-FAKE16-NEXT: v_pk_max_f16 v1, v1, v1 clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32_clamp_postcvt:
; GISEL-GFX900: ; %bb.0:
@@ -1342,17 +1419,33 @@ define <4 x half> @v_mad_mix_v4f32_clamp_postcvt(<4 x half> %src0, <4 x half> %s
; SDAG-CI-NEXT: v_or_b32_e32 v1, v3, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v4f32_clamp_postcvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v4f32_clamp_postcvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v1, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v6, v8, v9 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v7, v10, v11 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32_clamp_postcvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mix_v4f32_clamp_postcvt:
; GISEL-CI: ; %bb.0:
@@ -1502,14 +1595,23 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_lo(<2 x half> %src0, <2 x half>
; SDAG-CI-NEXT: v_or_b32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mix_v2f32_clamp_postcvt_lo:
; GISEL-CI: ; %bb.0:
@@ -1625,14 +1727,23 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_hi(<2 x half> %src0, <2 x half>
; SDAG-CI-NEXT: v_or_b32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_clamp_postcvt_hi:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_hi:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_postcvt_hi:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mix_v2f32_clamp_postcvt_hi:
; GISEL-CI: ; %bb.0:
@@ -1752,17 +1863,31 @@ define <2 x half> @v_mad_mix_v2f32_clamp_precvt(<2 x half> %src0, <2 x half> %sr
; SDAG-CI-NEXT: v_or_b32_e32 v0, v0, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_clamp_precvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v1, v3
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_pack_b32_f16 v0, v1, v0
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_precvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v3, v4, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_precvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v3
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_pack_b32_f16 v0, v1, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_clamp_precvt:
; GISEL-GFX900: ; %bb.0:
@@ -1913,22 +2038,38 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; SDAG-CI-NEXT: v_or_b32_e32 v0, v0, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v3f32_clamp_precvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v2, v3
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX1100-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_pack_b32_f16 v0, v2, v0
-; GISEL-GFX1100-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v3f32_clamp_precvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v6, v7, v8 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v6
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32_clamp_precvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_pack_b32_f16 v0, v2, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v3f32_clamp_precvt:
; GISEL-GFX900: ; %bb.0:
@@ -2116,23 +2257,45 @@ define <4 x half> @v_mad_mix_v4f32_clamp_precvt(<4 x half> %src0, <4 x half> %sr
; SDAG-CI-NEXT: v_or_b32_e32 v1, v1, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v4f32_clamp_precvt:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v1, v3, v5 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v3, v6
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GISEL-GFX1100-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_pack_b32_f16 v0, v3, v0
-; GISEL-GFX1100-NEXT: v_pack_b32_f16 v1, v2, v1
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v4f32_clamp_precvt:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v6, v7, v8 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v9, v10, v11 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v6
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v1
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32_clamp_precvt:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v6
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GISEL-GFX1100-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_pack_b32_f16 v0, v3, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_pack_b32_f16 v1, v2, v1
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v4f32_clamp_precvt:
; GISEL-GFX900: ; %bb.0:
@@ -2253,13 +2416,21 @@ define i32 @mixlo_zext(float %src0, float %src1, float %src2) #0 {
; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: mixlo_zext:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: mixlo_zext:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: mixlo_zext:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: mixlo_zext:
; GISEL-CI: ; %bb.0:
@@ -2487,6 +2658,6 @@ declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #
attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL-GFX1100-FAKE16: {{.*}}
+; GISEL-GFX1100: {{.*}}
; GISEL-VI: {{.*}}
; SDAG-VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index 4e1acf114da5d..7fb8443774b4f 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -7,8 +7,7 @@
; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=VI,SDAG-VI %s
; RUN: llc -mtriple=amdgpu7.01 < %s | FileCheck -check-prefixes=CI,SDAG-CI %s
-; FIXME-TRUE16. enable gisel
-; XUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-TRUE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GISEL-GFX1100,GISEL-GFX1100-FAKE16 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX900,GISEL-GFX900 %s
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.06 < %s | FileCheck -check-prefixes=GFX906,GISEL-GFX906 %s
@@ -191,14 +190,14 @@ define float @v_mad_mix_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %
}
define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_v2f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_v2f32:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v3
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32:
; GFX900: ; %bb.0:
@@ -257,6 +256,27 @@ define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x hal
; CI-NEXT: v_mac_f32_e32 v1, v5, v4
; CI-NEXT: v_mac_f32_e32 v0, v6, v7
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v3, v4, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext <2 x half> %src0 to <2 x float>
%src1.ext = fpext <2 x half> %src1 to <2 x float>
%src2.ext = fpext <2 x half> %src2 to <2 x float>
@@ -265,14 +285,14 @@ define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x hal
}
define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
-; GFX1100-LABEL: v_mad_mix_v2f32_shuffle:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_shuffle:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v3
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32_shuffle:
; GFX900: ; %bb.0:
@@ -330,6 +350,25 @@ define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x half> %src0, <2 x half> %src1,
; CI-NEXT: v_mad_f32 v0, v4, v0, v1
; CI-NEXT: v_mac_f32_e32 v1, v5, v2
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_shuffle:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v4, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_shuffle:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.shuf = shufflevector <2 x half> %src0, <2 x half> poison, <2 x i32> <i32 1, i32 0>
%src1.shuf = shufflevector <2 x half> %src1, <2 x half> poison, <2 x i32> <i32 0, i32 1>
%src2.shuf = shufflevector <2 x half> %src2, <2 x half> poison, <2 x i32> <i32 1, i32 1>
@@ -729,13 +768,13 @@ define float @v_mad_mix_f32_f16lo_f16lo_negabsf32(half %src0, half %src1, float
; inline immediate.
define float @v_mad_mix_f32_f16lo_f16lo_f32imm1(half %src0, half %src1) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: s_mov_b32 s0, 1.0
-; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: s_mov_b32 s0, 1.0
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
; GFX900: ; %bb.0:
@@ -774,6 +813,22 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imm1(half %src0, half %src1) #0 {
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_mad_f32 v0, v0, v1, 1.0
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v2, 1.0
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imm1:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 1.0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float 1.0)
@@ -781,13 +836,13 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imm1(half %src0, half %src1) #0 {
}
define float @v_mad_mix_f32_f16lo_f16lo_f32imminv2pi(half %src0, half %src1) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: s_mov_b32 s0, 0.15915494
-; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0.15915494
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
; GFX900: ; %bb.0:
@@ -827,6 +882,22 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imminv2pi(half %src0, half %src1) #0
; SDAG-CI-NEXT: v_madak_f32 v0, v0, v1, 0x3e22f983
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v2, 0.15915494
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 0.15915494
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_f16lo_f16lo_f32imminv2pi:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -848,13 +919,13 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32imminv2pi(half %src0, half %src1) #0
; f32 1/2pi = 0x3e22f983
define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi(half %src0, half %src1) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: s_mov_b32 s0, 0x3e230000
-; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0x3e230000
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
; GFX900: ; %bb.0:
@@ -894,6 +965,22 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi(half %src0, half %src1)
; SDAG-CI-NEXT: v_madak_f32 v0, v0, v1, 0x3e230000
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v2, 0x3e230000
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 0x3e230000
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -911,13 +998,13 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imminv2pi(half %src0, half %src1)
define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imm63(half %src0, half %src1) #0 {
-; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: s_mov_b32 s0, 0x367c0000
-; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0x367c0000
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
; GFX900: ; %bb.0:
@@ -957,6 +1044,22 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imm63(half %src0, half %src1) #0 {
; SDAG-CI-NEXT: v_madak_f32 v0, v0, v1, 0x367c0000
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v2, 0x367c0000
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: s_mov_b32 s0, 0x367c0000
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, s0 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_f16lo_f16lo_cvtf16imm63:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1036,15 +1139,28 @@ define <2 x float> @v_mad_mix_v2f32_f32imm1(<2 x half> %src0, <2 x half> %src1)
; CI-NEXT: v_mad_f32 v1, v3, v2, 1.0
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_f32imm1:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v3, 1.0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_f32imm1:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v3, 1.0
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v4, v3 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_f32imm1:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v3, 1.0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_f32imm1:
; GISEL-GFX900: ; %bb.0:
@@ -1136,15 +1252,28 @@ define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half>
; CI-NEXT: v_mac_f32_e32 v1, v3, v2
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v3, 0x3e230000
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v3, 0x3e230000
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v4, v3 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v3, 0x3e230000
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; GISEL-GFX900: ; %bb.0:
@@ -1235,15 +1364,28 @@ define <2 x float> @v_mad_mix_v2f32_f32imminv2pi(<2 x half> %src0, <2 x half> %s
; CI-NEXT: v_mac_f32_e32 v1, v3, v2
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_f32imminv2pi:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v3, 0.15915494
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_f32imminv2pi:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v3, 0.15915494
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v4, v3 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_f32imminv2pi:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v3, 0.15915494
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_f32imminv2pi:
; GISEL-GFX900: ; %bb.0:
@@ -1874,14 +2016,23 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo(i32 %src0.arg, half %
; CI-NEXT: v_mac_f32_e32 v0, v3, v1
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_xor_b16 v2.l, 0x8000, v0.h
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v2|, v1, v0 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 1
%src0.neg = fneg half %src0
@@ -2281,14 +2432,14 @@ define float @v_mad_mix_f32_f16hi_add_f16hi_elt(<2 x half> %src0, <2 x half> %sr
}
define <2 x float> @v_mad_mix_v2f32_cvt_add(<2 x half> %src0, <2 x half> %src1) {
-; GFX1100-LABEL: v_mad_mix_v2f32_cvt_add:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_mov_b32_e32 v0, v2
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_cvt_add:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32_cvt_add:
; GFX900: ; %bb.0:
@@ -2343,6 +2494,26 @@ define <2 x float> @v_mad_mix_v2f32_cvt_add(<2 x half> %src0, <2 x half> %src1)
; CI-NEXT: v_add_f32_e32 v1, v3, v2
; CI-NEXT: v_add_f32_e32 v0, v0, v4
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_cvt_add:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, 1.0, v3 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_cvt_add:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext <2 x half> %src0 to <2 x float>
%src1.ext = fpext <2 x half> %src1 to <2 x float>
%result = fadd <2 x float> %src0.ext, %src1.ext
@@ -2350,14 +2521,14 @@ define <2 x float> @v_mad_mix_v2f32_cvt_add(<2 x half> %src0, <2 x half> %src1)
}
define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_add(<2 x half> %src0, <2 x half> %src1) {
-; GFX1100-LABEL: v_mad_mix_v2f32_shuffle_cvt_add:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[0,0,1] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_mov_b32_e32 v0, v2
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_shuffle_cvt_add:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[0,0,1] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32_shuffle_cvt_add:
; GFX900: ; %bb.0:
@@ -2412,6 +2583,25 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_add(<2 x half> %src0, <2 x half>
; CI-NEXT: v_add_f32_e32 v0, v3, v0
; CI-NEXT: v_add_f32_e32 v1, v4, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_shuffle_cvt_add:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v3, 1.0, v1 op_sel:[0,0,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_shuffle_cvt_add:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[0,0,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.shuf = shufflevector <2 x half> %src0, <2 x half> poison, <2 x i32> <i32 1, i32 0>
%src1.shuf = shufflevector <2 x half> %src1, <2 x half> poison, <2 x i32> <i32 0, i32 1>
%src0.ext = fpext <2 x half> %src0.shuf to <2 x float>
@@ -2421,11 +2611,11 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_add(<2 x half> %src0, <2 x half>
}
define float @v_mad_mix_f32_negf16lo_add_f16lo(half %src0, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
; GFX900: ; %bb.0:
@@ -2465,6 +2655,18 @@ define float @v_mad_mix_f32_negf16lo_add_f16lo(half %src0, half %src1) {
; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2920,11 +3122,11 @@ define float @v_mad_mix_clamp_f32_f16hi_add_f16hi(<2 x half> %src0, <2 x half> %
}
define float @v_mad_mix_f32_negprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
; GFX900: ; %bb.0:
@@ -2964,6 +3166,18 @@ define float @v_mad_mix_f32_negprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1)
; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3034,11 +3248,11 @@ define float @v_mad_mix_f32_absprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_negabsprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
; GFX900: ; %bb.0:
@@ -3078,6 +3292,18 @@ define float @v_mad_mix_f32_negabsprecvtf16lo_add_f16lo(i32 %src0.arg, half %src
; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GISEL-CI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3155,14 +3381,23 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo(i32 %src0.arg, half %sr
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v1|, 1.0, v0 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 1
%src0.neg = fneg half %src0
@@ -3228,11 +3463,11 @@ define float @v_mad_mix_f32_precvtabsf16hi_add_f16lo(i32 %src0.arg, half %src1)
}
define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
; GFX900: ; %bb.0:
@@ -3272,6 +3507,18 @@ define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%fneg = fneg <2 x half> %src0.arg.bc
%src0 = extractelement <2 x half> %fneg, i32 1
@@ -3336,11 +3583,11 @@ define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %
}
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) {
-; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
; GFX900: ; %bb.0:
@@ -3380,6 +3627,18 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, ha
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
%fneg.fabs = fneg <2 x half> %fabs
@@ -3553,14 +3812,14 @@ define float @v_mad_mix_f32_f16hi_mul_f16hi_elt(<2 x half> %src0, <2 x half> %sr
}
define <2 x float> @v_mad_mix_v2f32_cvt_mul(<2 x half> %src0, <2 x half> %src1) {
-; GFX1100-LABEL: v_mad_mix_v2f32_cvt_mul:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_mov_b32_e32 v0, v2
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_cvt_mul:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32_cvt_mul:
; GFX900: ; %bb.0:
@@ -3615,6 +3874,26 @@ define <2 x float> @v_mad_mix_v2f32_cvt_mul(<2 x half> %src0, <2 x half> %src1)
; CI-NEXT: v_mul_f32_e32 v1, v3, v2
; CI-NEXT: v_mul_f32_e32 v0, v0, v4
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_cvt_mul:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v3, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_cvt_mul:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext <2 x half> %src0 to <2 x float>
%src1.ext = fpext <2 x half> %src1 to <2 x float>
%result = fmul <2 x float> %src0.ext, %src1.ext
@@ -3622,14 +3901,14 @@ define <2 x float> @v_mad_mix_v2f32_cvt_mul(<2 x half> %src0, <2 x half> %src1)
}
define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_mul(<2 x half> %src0, <2 x half> %src1) {
-; GFX1100-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[0,1,0] op_sel_hi:[1,1,0]
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_mov_b32_e32 v0, v2
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul:
+; SDAG-GFX1100: ; %bb.0:
+; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul:
; GFX900: ; %bb.0:
@@ -3684,6 +3963,25 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_mul(<2 x half> %src0, <2 x half>
; CI-NEXT: v_mul_f32_e32 v0, v3, v0
; CI-NEXT: v_mul_f32_e32 v1, v4, v1
; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v2, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v3, v1, neg(0) op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.shuf = shufflevector <2 x half> %src0, <2 x half> poison, <2 x i32> <i32 1, i32 0>
%src1.shuf = shufflevector <2 x half> %src1, <2 x half> poison, <2 x i32> <i32 0, i32 1>
%src0.ext = fpext <2 x half> %src0.shuf to <2 x float>
@@ -4412,14 +4710,23 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo(i32 %src0.arg, half %sr
; CI-NEXT: v_mul_f32_e32 v0, v0, v1
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo:
-; GISEL-GFX1100: ; %bb.0:
-; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-NEXT: v_xor_b32_e32 v0, 0x8000, v0
-; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
-; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo:
+; GISEL-GFX1100-TRUE16: ; %bb.0:
+; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v1|, v0, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo:
+; GISEL-GFX1100-FAKE16: ; %bb.0:
+; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
%src0 = extractelement <2 x half> %src0.arg.bc, i32 1
%src0.neg = fneg half %src0
@@ -4885,7 +5192,7 @@ attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind denormal_fpenv(float: ieee|ieee) }
attributes #2 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL-GFX1100-FAKE16: {{.*}}
+; GISEL-GFX1100: {{.*}}
; GISEL-GFX9GEN: {{.*}}
; GISEL-VI: {{.*}}
; SDAG-GFX9GEN: {{.*}}
>From 45d1db46690c588d02bbb274194cb270a18c83d8 Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Tue, 14 Jul 2026 16:48:03 -0400
Subject: [PATCH 2/2] Better, more generic approach to massaging 16bit
arguments into 32bit registers for fma mix instructions in GISEL
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 32 ++-
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll | 26 +-
llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll | 111 ++++-----
llvm/test/CodeGen/AMDGPU/mad-mix.ll | 234 +++++-------------
4 files changed, 157 insertions(+), 246 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 9547b07728ce5..2469bd6e3f18b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -7180,6 +7180,27 @@ AMDGPUInstructionSelector::selectSMRDBufferSgprImm(MachineOperand &Root) const {
[=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedOffset); }}};
}
+static Register createVOP3PSrc32FromLo16(Register Src, MachineInstr *MI,
+ MachineRegisterInfo &MRI,
+ const SIInstrInfo &TII,
+ const AMDGPUSubtarget &ST) {
+ MachineIRBuilder B(*MI);
+
+ // Create an vgpr_16 for the hi16 part using IMPLICIT_DEF
+ Register ImpdefReg = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
+ B.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(ImpdefReg);
+
+ Register DstReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ B.buildInstr(AMDGPU::REG_SEQUENCE)
+ .addDef(DstReg)
+ .addReg(Src)
+ .addImm(AMDGPU::lo16)
+ .addReg(ImpdefReg)
+ .addImm(AMDGPU::hi16);
+
+ return DstReg;
+}
+
std::pair<Register, unsigned>
AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
bool &Matched) const {
@@ -7225,13 +7246,10 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
Mods |= SISrcMods::OP_SEL_0;
CheckAbsNeg();
}
- // Since we looked through FPEXT and removed it, we must also remove
- // G_TRUNC. G_TRUNC to 16-bits would have a destination in RC VGPR_16, which
- // is not compatible with MadMix instructions
- Register PeekSrc = Src;
- if (Subtarget->useRealTrue16Insts() &&
- mi_match(PeekSrc, *MRI, m_GTrunc(m_Reg(PeekSrc))))
- Src = PeekSrc;
+
+ if (Subtarget->useRealTrue16Insts())
+ Src = createVOP3PSrc32FromLo16(Src, Root.getParent(), *MRI, TII,
+ *Subtarget);
Matched = true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index fa9854a2f4ea3..7a2956a7b95be 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -593,14 +593,24 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi
; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX11-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX11-NEXT: global_store_b16 v[0:1], v3, off dlc
-; GISEL-GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:
+; GISEL-GFX11-TRUE16: ; %bb.0:
+; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v1, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX11-TRUE16-NEXT: global_store_d16_hi_b16 v[0:1], v1, off dlc
+; GISEL-GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GISEL-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GISEL-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:
+; GISEL-GFX11-FAKE16: ; %bb.0:
+; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX11-FAKE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v3, off dlc
+; GISEL-GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GISEL-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:
; GISEL-CI: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
index 7392137287d97..fc5812c92a537 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
@@ -500,10 +500,9 @@ define <2 x half> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v3, v4, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, v4, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32:
@@ -633,13 +632,10 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v6, v7, v8 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v9, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v2, v4 op_sel_hi:[1,1,1]
; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v6, v7, v8 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32:
@@ -820,19 +816,16 @@ define <4 x half> @v_mad_mix_v4f32(<4 x half> %src0, <4 x half> %src1, <4 x half
; GISEL-GFX1100-TRUE16: ; %bb.0:
; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v6, v8, v9 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v2, v7, v10, v11 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v6
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v2, v4 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v6, v7, v8 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v1, v9, v10, v11 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32:
@@ -1002,9 +995,9 @@ define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %s
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v3, v4, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, v4, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_postcvt:
@@ -1179,13 +1172,14 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
; GISEL-GFX1100-TRUE16: ; %bb.0:
; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v6, v7, v8 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v6, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32_clamp_postcvt:
@@ -1423,16 +1417,17 @@ define <4 x half> @v_mad_mix_v4f32_clamp_postcvt(<4 x half> %src0, <4 x half> %s
; GISEL-GFX1100-TRUE16: ; %bb.0:
; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v1, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v6, v8, v9 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v7, v10, v11 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v0, v6, v7, v8 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v1, v9, v10, v11 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32_clamp_postcvt:
@@ -1866,15 +1861,11 @@ define <2 x half> @v_mad_mix_v2f32_clamp_precvt(<2 x half> %src0, <2 x half> %sr
; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_clamp_precvt:
; GISEL-GFX1100-TRUE16: ; %bb.0:
; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v3, v4, v5 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v3
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_clamp_precvt:
@@ -2041,17 +2032,14 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr
; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v3f32_clamp_precvt:
; GISEL-GFX1100-TRUE16: ; %bb.0:
; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v6, v7, v8 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v6
; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
-; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v6
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32_clamp_precvt:
@@ -2260,23 +2248,18 @@ define <4 x half> @v_mad_mix_v4f32_clamp_precvt(<4 x half> %src0, <4 x half> %sr
; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v4f32_clamp_precvt:
; GISEL-GFX1100-TRUE16: ; %bb.0:
; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v6, v6, v7, v8 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v9, v10, v11 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v4, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v0, v1, v3 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v6
-; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v1
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v3
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v4
+; GISEL-GFX1100-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v3
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v4f32_clamp_precvt:
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index 7fb8443774b4f..1927268657e57 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -190,14 +190,14 @@ define float @v_mad_mix_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %
}
define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
-; SDAG-GFX1100-LABEL: v_mad_mix_v2f32:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v3
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_v2f32:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-NEXT: v_mov_b32_e32 v0, v3
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32:
; GFX900: ; %bb.0:
@@ -256,27 +256,6 @@ define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x hal
; CI-NEXT: v_mac_f32_e32 v1, v5, v4
; CI-NEXT: v_mac_f32_e32 v0, v6, v7
; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32:
-; GISEL-GFX1100-TRUE16: ; %bb.0:
-; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v3, v4, v5 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32:
-; GISEL-GFX1100-FAKE16: ; %bb.0:
-; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
-; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext <2 x half> %src0 to <2 x float>
%src1.ext = fpext <2 x half> %src1 to <2 x float>
%src2.ext = fpext <2 x half> %src2 to <2 x float>
@@ -354,11 +333,12 @@ define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x half> %src0, <2 x half> %src1,
; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_shuffle:
; GISEL-GFX1100-TRUE16: ; %bb.0:
; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v4, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v3, v3, v1, v4 op_sel:[1,0,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_shuffle:
@@ -1139,28 +1119,15 @@ define <2 x float> @v_mad_mix_v2f32_f32imm1(<2 x half> %src0, <2 x half> %src1)
; CI-NEXT: v_mad_f32 v1, v3, v2, 1.0
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_f32imm1:
-; GISEL-GFX1100-TRUE16: ; %bb.0:
-; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v3, 1.0
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v4, v3 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_f32imm1:
-; GISEL-GFX1100-FAKE16: ; %bb.0:
-; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v3, 1.0
-; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_f32imm1:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v3, 1.0
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_f32imm1:
; GISEL-GFX900: ; %bb.0:
@@ -1252,28 +1219,15 @@ define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half>
; CI-NEXT: v_mac_f32_e32 v1, v3, v2
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
-; GISEL-GFX1100-TRUE16: ; %bb.0:
-; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v3, 0x3e230000
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v4, v3 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
-; GISEL-GFX1100-FAKE16: ; %bb.0:
-; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v3, 0x3e230000
-; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v3, 0x3e230000
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; GISEL-GFX900: ; %bb.0:
@@ -1364,28 +1318,15 @@ define <2 x float> @v_mad_mix_v2f32_f32imminv2pi(<2 x half> %src0, <2 x half> %s
; CI-NEXT: v_mac_f32_e32 v1, v3, v2
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_f32imminv2pi:
-; GISEL-GFX1100-TRUE16: ; %bb.0:
-; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v3, 0.15915494
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v4, v3 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_f32imminv2pi:
-; GISEL-GFX1100-FAKE16: ; %bb.0:
-; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v3, 0.15915494
-; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_f32imminv2pi:
+; GISEL-GFX1100: ; %bb.0:
+; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v3, 0.15915494
+; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_f32imminv2pi:
; GISEL-GFX900: ; %bb.0:
@@ -2432,14 +2373,14 @@ define float @v_mad_mix_f32_f16hi_add_f16hi_elt(<2 x half> %src0, <2 x half> %sr
}
define <2 x float> @v_mad_mix_v2f32_cvt_add(<2 x half> %src0, <2 x half> %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_cvt_add:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1]
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_v2f32_cvt_add:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel_hi:[1,1,1]
+; GFX1100-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1]
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32_cvt_add:
; GFX900: ; %bb.0:
@@ -2494,26 +2435,6 @@ define <2 x float> @v_mad_mix_v2f32_cvt_add(<2 x half> %src0, <2 x half> %src1)
; CI-NEXT: v_add_f32_e32 v1, v3, v2
; CI-NEXT: v_add_f32_e32 v0, v0, v4
; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_cvt_add:
-; GISEL-GFX1100-TRUE16: ; %bb.0:
-; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, 1.0, v3 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_cvt_add:
-; GISEL-GFX1100-FAKE16: ; %bb.0:
-; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel_hi:[1,1,1]
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext <2 x half> %src0 to <2 x float>
%src1.ext = fpext <2 x half> %src1 to <2 x float>
%result = fadd <2 x float> %src0.ext, %src1.ext
@@ -2587,11 +2508,11 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_add(<2 x half> %src0, <2 x half>
; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_shuffle_cvt_add:
; GISEL-GFX1100-TRUE16: ; %bb.0:
; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v3, 1.0, v1 op_sel:[0,0,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[0,0,1] op_sel_hi:[1,1,1]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_shuffle_cvt_add:
@@ -3812,14 +3733,14 @@ define float @v_mad_mix_f32_f16hi_mul_f16hi_elt(<2 x half> %src0, <2 x half> %sr
}
define <2 x float> @v_mad_mix_v2f32_cvt_mul(<2 x half> %src0, <2 x half> %src1) {
-; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_cvt_mul:
-; SDAG-GFX1100: ; %bb.0:
-; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; SDAG-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
-; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX1100-LABEL: v_mad_mix_v2f32_cvt_mul:
+; GFX1100: ; %bb.0:
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0]
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-NEXT: v_mov_b32_e32 v0, v2
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-LABEL: v_mad_mix_v2f32_cvt_mul:
; GFX900: ; %bb.0:
@@ -3874,26 +3795,6 @@ define <2 x float> @v_mad_mix_v2f32_cvt_mul(<2 x half> %src0, <2 x half> %src1)
; CI-NEXT: v_mul_f32_e32 v1, v3, v2
; CI-NEXT: v_mul_f32_e32 v0, v0, v4
; CI-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_cvt_mul:
-; GISEL-GFX1100-TRUE16: ; %bb.0:
-; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v3, neg(0) op_sel_hi:[1,1,0]
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_cvt_mul:
-; GISEL-GFX1100-FAKE16: ; %bb.0:
-; GISEL-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel_hi:[1,1,0]
-; GISEL-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext <2 x half> %src0 to <2 x float>
%src1.ext = fpext <2 x half> %src1 to <2 x float>
%result = fmul <2 x float> %src0.ext, %src1.ext
@@ -3967,11 +3868,11 @@ define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_mul(<2 x half> %src0, <2 x half>
; GISEL-GFX1100-TRUE16-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul:
; GISEL-GFX1100-TRUE16: ; %bb.0:
; GISEL-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v2, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
-; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v3, v1, neg(0) op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GISEL-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v2, v2, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[0,1,0] op_sel_hi:[1,1,0]
+; GISEL-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-FAKE16-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul:
@@ -5192,7 +5093,6 @@ attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind denormal_fpenv(float: ieee|ieee) }
attributes #2 = { nounwind readnone speculatable }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GISEL-GFX1100: {{.*}}
; GISEL-GFX9GEN: {{.*}}
; GISEL-VI: {{.*}}
; SDAG-GFX9GEN: {{.*}}
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