[llvm] [AMDGPU][CodeGen] Place `S_NOP` after `S_SETREG_IMM32_B32` in predecessor MBB (PR #209620)

[Jay Foad via llvm-commits]

================
@@ -432,23 +433,41 @@ AMDGPULowerVGPREncoding::handleCoissue(MachineBasicBlock::instr_iterator I) {
   return I;
 }
 
+/// Returns whether \p MI is a S_SETREG_IMM32_B32(MODE).
+static bool isSetregMode(const MachineInstr &MI, const SIInstrInfo &TII) {
+  if (MI.getOpcode() != AMDGPU::S_SETREG_IMM32_B32)
+    return false;
+
+  const MachineOperand *SIMM16Op =
+      TII.getNamedOperand(MI, AMDGPU::OpName::simm16);
+  auto [HwRegId, _Offset, _Size] =
+      AMDGPU::Hwreg::HwregEncoding::decode(SIMM16Op->getImm());
+  return HwRegId == AMDGPU::Hwreg::ID_MODE;
+}
+
 bool AMDGPULowerVGPREncoding::needNopBeforeSetVGPRMSB(
     MachineBasicBlock::instr_iterator I) {
-  while (I != MBB->begin()) {
-    I = std::prev(I);
-    if (I->getOpcode() == AMDGPU::S_SETREG_IMM32_B32) {
-      MachineOperand *SIMM16Op =
-          TII->getNamedOperand(*I, AMDGPU::OpName::simm16);
-      auto [HwRegId, Offset, Size] =
-          AMDGPU::Hwreg::HwregEncoding::decode(SIMM16Op->getImm());
-      if (HwRegId == AMDGPU::Hwreg::ID_MODE)
+  MachineBasicBlock *CurrentMBB = MBB;
+  while (true) {
+    // Walk the block backward until we hit a non-meta instruction or the
+    // beginning of the block.
+    while (I != CurrentMBB->instr_begin()) {
+      I = std::prev(I);
+      if (isSetregMode(*I, *TII))
         return true;
+      if (!I->isMetaInstruction())
+        return false;
     }
-    if (!I->isMetaInstruction())
+
+    // Look for a potential fallthrough predecessor block. When it ends with a
+    // S_SETREG_IMM32_B32(MODE) we need to insert a S_NOP too. We assume that an
+    // explicit jump to the current block from the block that would otherwise
+    // have naturally fell through to it will remain in the final assembly.
----------------
jayfoad wrote:

Grammar nit :)
```suggestion
    // have naturally fallen through to it will remain in the final assembly.
```

https://github.com/llvm/llvm-project/pull/209620