[llvm] [AArch64][SVE] Support lowering masked loads/stores of <4 x bf16> and <8 x bf16> (PR #208744)

[Shanzhi Chen via llvm-commits]

================

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chenshanzhi wrote:

Actually, it seems branches are still used without `+bf16`.

Currently, the results of f0, f1, f2 are all the same in the code below. 

I'm not sure whether this is what we desired or this is just another missing part of bf16.
I guess the results of f0 and f2 should be the same (i.e. using branches); the results of f1 and f3 should be the same (i.e. using SVE p-registers).

So I prefer to not include a test without `+bf16` (i.e. f1) in this PR.
But I would change the commit message to:
> Add support for lowering masked loads/stores of <4 x bf16> and <8 x bf16> when target features contain "+sve" and "+bf16".

https://godbolt.org/z/7Gdao595j

```llvm
target triple = "aarch64-none-linux-gnu"

define void @f0(ptr %p, <8 x i1> %cmp) #0 {
entry:
  tail call void @llvm.masked.store.v8bf16.p0(<8 x bfloat> zeroinitializer, ptr %p, <8 x i1> %cmp)
  ret void
}

define void @f1(ptr %p, <8 x i1> %cmp) #1 {
entry:
  tail call void @llvm.masked.store.v8bf16.p0(<8 x bfloat> zeroinitializer, ptr %p, <8 x i1> %cmp)
  ret void
}

define void @f2(ptr %p, <8 x i1> %cmp) #2 {
entry:
  tail call void @llvm.masked.store.v8bf16.p0(<8 x bfloat> zeroinitializer, ptr %p, <8 x i1> %cmp)
  ret void
}

; define void @f3(ptr %p, <8 x i1> %cmp) #3 {
; entry:
;   tail call void @llvm.masked.store.v8bf16.p0(<8 x bfloat> zeroinitializer, ptr %p, <8 x i1> %cmp)
;   ret void
; }


define void @g0(ptr %p, <8 x i1> %cmp) #0 {
entry:
  tail call void @llvm.masked.store.v8f16.p0(<8 x half> zeroinitializer, ptr %p, <8 x i1> %cmp)
  ret void
}

define void @g1(ptr %p, <8 x i1> %cmp) #1 {
entry:
  tail call void @llvm.masked.store.v8f16.p0(<8 x half> zeroinitializer, ptr %p, <8 x i1> %cmp)
  ret void
}

define void @g2(ptr %p, <8 x i1> %cmp) #2 {
entry:
  tail call void @llvm.masked.store.v8f16.p0(<8 x half> zeroinitializer, ptr %p, <8 x i1> %cmp)
  ret void
}

define void @g3(ptr %p, <8 x i1> %cmp) #3 {
entry:
  tail call void @llvm.masked.store.v8f16.p0(<8 x half> zeroinitializer, ptr %p, <8 x i1> %cmp)
  ret void
}


attributes #0 = { "target-features"="" }
attributes #1 = { "target-features"="+sve" }
attributes #2 = { "target-features"="+bf16" }
attributes #3 = { "target-features"="+sve,+bf16" }
```

https://github.com/llvm/llvm-project/pull/208744