[llvm] [X86] Select i8 ANDN via i32 promotion (PR #205050)

[via llvm-commits]

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@@ -51954,6 +51954,52 @@ static SDValue combineAndNotIntoANDNP(SDNode *N, const SDLoc &DL,
   return DAG.getNode(X86ISD::ANDNP, DL, VT, X, Y);
 }
 
+static SDValue combineI8AndNotIntoI32AndNot(SDNode *N, const SDLoc &DL,
+                                            SelectionDAG &DAG,
+                                            const X86Subtarget &Subtarget) {
+  assert(N->getOpcode() == ISD::AND && "Unexpected opcode combine into ANDN");
+
+  if (!Subtarget.hasBMI() || N->getValueType(0) != MVT::i8)
+    return SDValue();
+
+  // Keep compare and mask-lowering idioms in their existing byte forms.
+  for (SDUse &Use : N->uses()) {
+    if (Use.getResNo() != 0)
+      continue;
+    SDNode *User = Use.getUser();
+    if (User->getOpcode() == ISD::SETCC)
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mygitljf wrote:

Yes. This is covered by `blcic_v8i64` in
`llvm/test/CodeGen/X86/avx512-mask-bit-manip.ll`. Its checks retain the byte operations before `kmov`, exercising the BITCAST-to-vector-i1 exclusion.

https://github.com/llvm/llvm-project/pull/205050