[llvm] [AMDGPU] Post-RA Peephole for Two-Address Instructions (PR #207731)

[Lukas Sommer via llvm-commits]

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@@ -803,6 +1016,36 @@ bool SIPreEmitPeephole::run(MachineFunction &MF, MachineLoopInfo *LoopInfo) {
       }
     }
 
+    // Delayed optimization to replace two-address instructions followed by
+    // copies with a three-address instruction that directly writes to the
+    // copied registers instead. The pattern we seek to optimize is:
+    // $vgpr2_vgpr3 = V_FMAC_F64 ..., $vgpr_2_vgpr3
+    // $vgpr0 = V_MOV_B32 $vgrp2
+    // $vgpr1 = V_MOV_B32 $vgrp3
+    //
+    // This can be optimized to:
+    // $vgpr0_vgpr1 = V_FMA_F64 ..., $vgpr2_vgpr3
+    //
+    // The TwoAddressInstruction pass handles some cases, but bails in more
+    // complex cases.
+    SmallVector<ThreeAddressCandidate> Candidates;
+    // First, collect the candidates. We can't perform the transformation right
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sommerlukas wrote:

Even with `make_early_inc_range`, we can only delete the current instruction safely. As we also delete the copies during the transformation (which are later in the block), performing the transformation while iterating would not be safe.

https://github.com/llvm/llvm-project/pull/207731