[llvm] a208080 - [NFC][AMDGPU] Use SIInstrFlags predicates in MC layer (#206766)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 15 02:52:11 PDT 2026
Author: Valery Pykhtin
Date: 2026-07-15T11:52:05+02:00
New Revision: a208080eff277fc4829f3519e1f918aa4eb6adeb
URL: https://github.com/llvm/llvm-project/commit/a208080eff277fc4829f3519e1f918aa4eb6adeb
DIFF: https://github.com/llvm/llvm-project/commit/a208080eff277fc4829f3519e1f918aa4eb6adeb.diff
LOG: [NFC][AMDGPU] Use SIInstrFlags predicates in MC layer (#206766)
Replace raw TSFlags accesses with SIInstrFlags predicate calls in
AMDGPUInstPrinter and AMDGPUMCCodeEmitter.
Part of a series following the introduction of SIInstrFlags predicates.
Added:
Modified:
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/SIDefines.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 9687f31b298ad..2764ff2d68ce0 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -111,8 +111,7 @@ void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
O << " offset:";
// GFX12+ uses a 24-bit signed offset for VBUFFER.
- const MCInstrDesc &Desc = MII.get(MI->getOpcode());
- bool IsVBuffer = Desc.TSFlags & (SIInstrFlags::MUBUF | SIInstrFlags::MTBUF);
+ bool IsVBuffer = SIInstrFlags::isBuffer(MII, *MI);
if (IsVBuffer && AMDGPU::isGFX12Plus(STI))
O << formatDec(SignExtend32<24>(Imm));
else
@@ -127,9 +126,7 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
if (Imm != 0) {
O << " offset:";
- const MCInstrDesc &Desc = MII.get(MI->getOpcode());
- bool AllowNegative = (Desc.TSFlags & (SIInstrFlags::FlatGlobal |
- SIInstrFlags::FlatScratch)) ||
+ bool AllowNegative = SIInstrFlags::isSegmentSpecificFLAT(MII, *MI) ||
STI.hasFeature(AMDGPU::FeatureFlatSignedOffset);
if (AllowNegative) // Signed offset
@@ -422,19 +419,18 @@ void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, unsigned Opc,
void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
auto Opcode = MI->getOpcode();
- auto Flags = SIInstrFlags::getTSFlags(MII, Opcode);
if (OpNo == 0) {
- if (Flags & SIInstrFlags::VOP3 && Flags & SIInstrFlags::DPP)
+ if (SIInstrFlags::isVOP3(MII, *MI) && SIInstrFlags::isDPP(MII, *MI))
O << "_e64_dpp";
- else if (Flags & SIInstrFlags::VOP3) {
+ else if (SIInstrFlags::isVOP3(MII, *MI)) {
if (!getVOP3IsSingle(Opcode))
O << "_e64";
- } else if (Flags & SIInstrFlags::DPP)
+ } else if (SIInstrFlags::isDPP(MII, *MI))
O << "_dpp";
- else if (Flags & SIInstrFlags::SDWA)
+ else if (SIInstrFlags::isSDWA(MII, *MI))
O << "_sdwa";
- else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
- ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode)))
+ else if ((SIInstrFlags::isVOP1(MII, *MI) && !getVOP1IsSingle(Opcode)) ||
+ (SIInstrFlags::isVOP2(MII, *MI) && !getVOP2IsSingle(Opcode)))
O << "_e32";
O << " ";
}
@@ -789,8 +785,7 @@ void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
unsigned OpNo) const {
- return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) &&
- (Desc.TSFlags & SIInstrFlags::VOPC) &&
+ return OpNo == 0 && SIInstrFlags::isDPP(Desc) && SIInstrFlags::isVOPC(Desc) &&
!isVOPCAsmOnly(Desc.getOpcode()) &&
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
@@ -806,9 +801,8 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
// 0, 1 and 2 are the first printed operands in
diff erent cases
// If there are printed modifiers, printOperandAndFPInputMods or
// printOperandAndIntInputMods will be called instead
- if ((OpNo == 0 ||
- (OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP) && ModIdx != -1)) &&
- (Desc.TSFlags & SIInstrFlags::VOPC) && !isVOPCAsmOnly(Desc.getOpcode()) &&
+ if ((OpNo == 0 || (OpNo == 1 && SIInstrFlags::isDPP(Desc) && ModIdx != -1)) &&
+ SIInstrFlags::isVOPC(Desc) && !isVOPCAsmOnly(Desc.getOpcode()) &&
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
printDefaultVccOperand(true, STI, O);
@@ -984,7 +978,7 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
break;
}
- if (Desc.TSFlags & SIInstrFlags::MTBUF) {
+ if (SIInstrFlags::isMTBUF(Desc)) {
int SOffsetIdx =
AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
assert(SOffsetIdx != -1);
@@ -1370,8 +1364,7 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
// Print three values of neg/opsel for wmma instructions (prints 0 when there
// is no src_modifier operand instead of not printing anything).
- if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsSWMMAC ||
- MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsWMMA) {
+ if (SIInstrFlags::isSWMMAC(MII, *MI) || SIInstrFlags::isWMMA(MII, *MI)) {
NumOps = 0;
int DefaultValue = Mod == SISrcMods::OP_SEL_1;
for (AMDGPU::OpName OpName :
@@ -1385,12 +1378,10 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
}
}
- const bool HasDstSel =
- HasDst && NumOps > 0 && Mod == SISrcMods::OP_SEL_0 &&
- MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
+ const bool HasDstSel = HasDst && NumOps > 0 && Mod == SISrcMods::OP_SEL_0 &&
+ SIInstrFlags::hasVOP3OpSel(MII, *MI);
- const bool IsPacked =
- MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
+ const bool IsPacked = SIInstrFlags::isPacked(MII, *MI);
if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
return;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index b3fdf38b9a688..0fd174bcde297 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -262,9 +262,8 @@ static uint32_t getLit64Encoding(const MCInstrDesc &Desc, uint64_t Val,
// The rest part needs to align with AMDGPUInstPrinter::printLiteral64.
- bool CanUse64BitLiterals =
- STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
- !(Desc.TSFlags & (SIInstrFlags::VOP3 | SIInstrFlags::VOP3P));
+ bool CanUse64BitLiterals = STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
+ !SIInstrFlags::isVOP3Like(Desc);
if (IsFP) {
return CanUse64BitLiterals && Lo_32(Val) ? 254 : 255;
}
@@ -404,8 +403,7 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
// Set unused op_sel_hi bits to 1 for VOP3P and MAI instructions.
// Note that accvgpr_read/write are MAI, have src0, but do not use op_sel.
- if (((Desc.TSFlags & SIInstrFlags::VOP3P) ||
- Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||
+ if ((SIInstrFlags::isVOP3P(Desc) || Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||
Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) &&
// Matrix B format operand reuses op_sel_hi.
!AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::matrix_b_fmt) &&
@@ -421,7 +419,7 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
}
// NSA encoding.
- if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
+ if (AMDGPU::isGFX10Plus(STI) && SIInstrFlags::isMIMG(Desc)) {
int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
AMDGPU::OpName::vaddr0);
int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
@@ -759,9 +757,8 @@ APInt AMDGPUMCCodeEmitter::postEncodeVOPCX(const MCInst &MI, APInt EncodedValue,
// is ignored by HW. It was decided to define dst as "do not care"
// in td files to allow disassembler accept any dst value.
// However, dst is encoded as EXEC for compatibility with SP3.
- [[maybe_unused]] const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
- assert((Desc.TSFlags & SIInstrFlags::VOP3) &&
- Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC));
+ assert(SIInstrFlags::isVOP3(MCII, MI) &&
+ MCII.get(MI.getOpcode()).hasImplicitDefOfPhysReg(AMDGPU::EXEC));
EncodedValue |= MRI.getEncodingValue(AMDGPU::EXEC_LO) &
AMDGPU::HWEncoding::LO256_REG_IDX_MASK;
return postEncodeVOP3<true, true, false>(MI, EncodedValue, STI);
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index ffaf9fb9e573a..61e3a095750d1 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -237,6 +237,9 @@ template <typename... T> constexpr bool isVOP3(const T &...O) {
template <typename... T> constexpr bool isVOP3P(const T &...O) {
return getTSFlags(O...) & VOP3P;
}
+template <typename... T> constexpr bool isVOP3Like(const T &...O) {
+ return getTSFlags(O...) & (VOP3 | VOP3P);
+}
template <typename... T> constexpr bool isVINTRP(const T &...O) {
return getTSFlags(O...) & VINTRP;
}
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