[llvm] [AMDGPU] Emit format opcodes for i8 buffer.{load, store}.format in SDAG (PR #209703)

[Matt Arsenault via llvm-commits]

================
@@ -608,6 +608,45 @@ main_body:
   ret float %fdata
 }
 
+define amdgpu_ps float @buffer_load_x_i8(ptr addrspace(8) inreg %rsrc) {
+; GFX6-LABEL: buffer_load_x_i8:
+; GFX6:       ; %bb.0: ; %main_body
+; GFX6-NEXT:    v_mov_b32_e32 v0, 0
+; GFX6-NEXT:    buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; GFX6-NEXT:    s_waitcnt vmcnt(0)
+; GFX6-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_x_i8:
+; GFX8PLUS:       ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT:    v_mov_b32_e32 v0, 0
+; GFX8PLUS-NEXT:    buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; GFX8PLUS-NEXT:    s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX8PLUS-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_x_i8:
+; GFX11:       ; %bb.0: ; %main_body
+; GFX11-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-NEXT:    buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT:    ; return to shader part epilog
+;
+; NOPRT-LABEL: buffer_load_x_i8:
+; NOPRT:       ; %bb.0: ; %main_body
+; NOPRT-NEXT:    v_mov_b32_e32 v0, 0
+; NOPRT-NEXT:    buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; NOPRT-NEXT:    s_waitcnt vmcnt(0)
+; NOPRT-NEXT:    v_and_b32_e32 v0, 0xff, v0
+; NOPRT-NEXT:    ; return to shader part epilog
+main_body:
+  %data = call i8 @llvm.amdgcn.struct.ptr.buffer.load.format.i8(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 0)
----------------
arsenm wrote:

I wouldn't expect this to select at all. It doesn't correspond to a real instruction 

https://github.com/llvm/llvm-project/pull/209703