[llvm] [BOLT][RISCV] Fix conditional tail call (PR #209474)

[via llvm-commits]

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@@ -328,6 +336,8 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
     default:
       return false;
     case RISCV::C_J:
+    case RISCV::PseudoCALL:
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Thrrreeee wrote:

They are not produced by disassembly, but BOLT creates them internally. `createCall()` and `createTailCall()` will creates a PseudoCALL/PseudoTAIL. These instructions remain in BOLT’s MCInst stream until the RISC-V MC emitter expands them into AUIPC/JALR.

https://github.com/llvm/llvm-project/pull/209474