[llvm] [AMDGPU] Post-RA Peephole for Two-Address Instructions (PR #207731)

[Carl Ritson via llvm-commits]

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@@ -763,13 +802,185 @@ MachineInstrBuilder SIPreEmitPeephole::createUnpackedMI(MachineInstr &I,
   return NewMI;
 }
 
+bool SIPreEmitPeephole::isLateThreeAddrPeepholeCandidate(
+    const MachineInstr &MI) const {
+  // This is a subset of the opcodes that are convertible to three-address
+  // instructions according to . This is intended. For some cases,
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perlfu wrote:

"according to ." ?

https://github.com/llvm/llvm-project/pull/207731