[llvm] [AMDGPU] Post-RA Peephole for Two-Address Instructions (PR #207731)

[Carl Ritson via llvm-commits]

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@@ -81,8 +83,42 @@ class SIPreEmitPeephole {
   void addOperandAndMods(MachineInstrBuilder &NewMI, unsigned SrcMods,
                          bool IsHiBits, const MachineOperand &SrcMO);
 
+  // Hold information about a candidate for delayed post-RA conversion from a
+  // two-address instruction to a three-address instruction. The copy
+  // instructions become redundant after retargeting the converted instruction
+  // to NewDst.
+  struct ThreeAddressCandidate {
+    MachineInstr *TwoAddrMI;
+    Register NewDst;
+    SmallVector<MachineInstr *, 2> CopiesToRemove;
+
+    ThreeAddressCandidate(MachineInstr &TwoAddrMI, Register NewDst,
+                          ArrayRef<MachineInstr *> Copies)
+        : TwoAddrMI(&TwoAddrMI), NewDst(NewDst), CopiesToRemove(Copies) {}
+  };
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perlfu wrote:

This is a nit, but can you put whitespace before the comment describing functions to improve readability?

https://github.com/llvm/llvm-project/pull/207731