[llvm] [AArch64][SVE] Support lowering masked loads/stores of <4 x bf16> and <8 x bf16> (PR #208744)

[Shanzhi Chen via llvm-commits]

chenshanzhi wrote:

> Hi - I happened to be looking into fixing this yesterday morning before I saw there was already a draft PR. We probably want this on the branch but I am unsure about the change in useSVEForFixedLengthVectorVT - it makes all kinds of changes with legal types and we could do with a more limited version in the short term. Can we pass allowBF16 into useSVEForFixedLengthVectorVT as parameter and use it just for the MLoad?

Yes. I agree that adding a parameter `AllowBF`  to `useSVEForFixedLengthVectorVT` is a better approach. It makes future incremental changes much easier. Changed in 2e1784c1ef15adb96f052b7c57dc3e06a9c4311d as suggested. Thanks for the review comments!

While analyzing the test cases for code generation involving vectors of bf16, I noticed that there is indeed some room for improvement. Great news for a beginner like me! As I want to learn and contribute more about the AArch64 backend in LLVM, I may take some time to investigate and work on some of them in the future.

https://github.com/llvm/llvm-project/pull/208744