[llvm] test (PR #209608)

[Guo Chen via llvm-commits]

https://github.com/broxigarchen created https://github.com/llvm/llvm-project/pull/209608

None

>From be7a2e5ae30617027cc58996158ed2429478b95d Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 14 Jul 2026 12:24:00 -0400
Subject: [PATCH] test

---
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 18 ++++++++++++++++++
 llvm/lib/Target/AMDGPU/SIRegisterInfo.h   |  5 +++++
 2 files changed, 23 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 619db2f61e0e9..8c775a78d3528 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -4328,3 +4328,21 @@ SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
     RegFlags.push_back("WWM_REG");
   return RegFlags;
 }
+
+bool SIRegisterInfo::shouldCoalesce(
+    MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
+    const TargetRegisterClass *DstRC, unsigned DstSubReg,
+    const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
+  assert(MI->isCopy() && "Only expecting COPY instructions");
+
+  // Do not coalesce if src is a constant, let RA decide if need to
+  // rematerialize
+  MachineFunction *MF = MI->getParent()->getParent();
+  MachineRegisterInfo &MRI = MF->getRegInfo();
+  MachineInstr *Def = MRI.getUniqueVRegDef(MI->getOperand(1).getReg());
+  if (Def && Def->isMoveImmediate())
+    return false;
+
+  return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg,
+                                            NewRC, LIS);
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index e464c9334ffea..01a94f56382d7 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -506,6 +506,11 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
                 ? 2.0
                 : 1.0);
   }
+
+  bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
+                      unsigned SubReg, const TargetRegisterClass *DstRC,
+                      unsigned DstSubReg, const TargetRegisterClass *NewRC,
+                      LiveIntervals &LIS) const override;
 };
 
 } // End namespace llvm