[llvm] 3ba1b70 - [AMDGPU][CodeGen] Fix `S_NOP` insertion during `S_SET_VGPR_MSB` placement (#209525)

[via llvm-commits]

Author: Lucas Ramirez
Date: 2026-07-14T21:55:04+02:00
New Revision: 3ba1b70dc2f4920d727ec1e678a79b744ce72b99

URL: https://github.com/llvm/llvm-project/commit/3ba1b70dc2f4920d727ec1e678a79b744ce72b99
DIFF: https://github.com/llvm/llvm-project/commit/3ba1b70dc2f4920d727ec1e678a79b744ce72b99.diff

LOG: [AMDGPU][CodeGen] Fix `S_NOP` insertion during `S_SET_VGPR_MSB` placement (#209525)

The issue arises when co-issue optimizations move the initial insertion
position for `S_SET_VGPR_MSB` to an earlier spot, creating a mismatch
with the position used to determine whether a `S_NOP` is needed.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
    llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
index 3510e2b1bc2b5..f6c981ad464ab 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
@@ -254,7 +254,7 @@ bool AMDGPULowerVGPREncoding::setMode(ModeTy NewMode,
   // current MSBs, but the next VALU needs 
diff erent MSBs, so this
   // S_SET_VGPR_MSB would land right after the setreg. Insert S_NOP to
   // prevent it from being silently dropped.
-  if (needNopBeforeSetVGPRMSB(I))
+  if (needNopBeforeSetVGPRMSB(InsertPt))
     BuildMI(*MBB, InsertPt, {}, TII->get(AMDGPU::S_NOP)).addImm(0);
   MostRecentModeSet =
       BuildMI(*MBB, InsertPt, {}, TII->get(AMDGPU::S_SET_VGPR_MSB))

diff  --git a/llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir b/llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
index 6a19313e78872..9aeb1a0a49c38 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir
@@ -134,6 +134,7 @@ body:             |
     ; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
     ; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 $vgpr257, implicit $exec
     ; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
+    ; CHECK-NEXT: S_NOP 0
     ; CHECK-NEXT: S_SET_VGPR_MSB 16713, implicit-def $mode
     ; CHECK-NEXT: S_BARRIER_WAIT -1
     ; CHECK-NEXT: $vgpr256 = V_ADD_U32_e32 $vgpr257, $vgpr512, implicit $exec