[llvm] [LoadStoreVectorizer] Support vectorization of mixed-type contiguous accesses (PR #177908)

[Anshil Gandhi via llvm-commits]

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@@ -555,13 +623,67 @@ bool Vectorizer::runOnChain(Chain &C) {
   // all at worst O(n lg n) in the number of instructions, and splitting chains
   // doesn't change the number of instrs.  So the whole loop nest is O(n lg n).)
   bool Changed = false;
-  for (auto &C : splitChainByMayAliasInstrs(C))
-    for (auto &C : splitChainByContiguity(C))
-      for (auto &C : splitChainByAlignment(C))
-        Changed |= vectorizeChain(C);
+  for (auto &C : splitChainByPointerWidth(C))
+    for (auto &C : splitChainByMayAliasInstrs(C))
+      for (auto &C : splitChainByContiguity(C))
+        for (auto &C : splitChainByAlignment(C))
+          Changed |= vectorizeChain(C);
   return Changed;
 }
 
+std::vector<Chain> Vectorizer::splitChainByPointerWidth(Chain &C) {
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gandhi56 wrote:

Machine IR has strict rules for virtual registers as they are assigned register classes. That is, the only way to bitcast a value is if the subtarget supports to do so via it's ISA. Therefore, the introduction of the byte type does not really affect the backend as they are mapped to a string of bits anyways. None of the SelectionDAG tests failed due to the use of the byte type in this patch.

https://github.com/llvm/llvm-project/pull/177908