[llvm] [AArch64] Add combine for interleave deinterleave (3/n) (PR #208414)

[Kamlesh Kumar via llvm-commits]

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@@ -0,0 +1,66 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -lower-interleaved-accesses=false < %s | FileCheck --check-prefix=AS %s
+
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
+target triple = "arm64--linux-gnu"
+
+define void @aarch64_vector_interleave_idx_st2(ptr %ptr, i64 %idx, <4 x float> %v0, <4 x float> %v1) {
+; AS-LABEL: aarch64_vector_interleave_idx_st2:
+; AS:       // %bb.0: // %entry
+; AS-NEXT:    lsr x8, x1, #2
+; AS-NEXT:    zip2 v2.4s, v0.4s, v1.4s
+; AS-NEXT:    zip1 v0.4s, v0.4s, v1.4s
+; AS-NEXT:    add x8, x0, x8, lsl #4
+; AS-NEXT:    stp q0, q2, [x8]
+; AS-NEXT:    ret
+entry:
+  %idx1 = lshr i64 %idx, 2
+  %gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx1
+
+  %interleave = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %v0, <4 x float> %v1)
+  store <8 x float> %interleave, ptr %gep1, align 16
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kamleshbhalui wrote:

Now I have stacked the PR, and ld2/dt2 is visible

https://github.com/llvm/llvm-project/pull/208414