[llvm] aefba88 - [LLVM][CodeGen][SVE] Add isel for zext(setcc(x,0,ne)) -> umin(x,1). (#209452)

[via llvm-commits]

Author: Paul Walker
Date: 2026-07-14T14:22:21+01:00
New Revision: aefba88f46a6e55645c848f58f6ba56944d5ae62

URL: https://github.com/llvm/llvm-project/commit/aefba88f46a6e55645c848f58f6ba56944d5ae62
DIFF: https://github.com/llvm/llvm-project/commit/aefba88f46a6e55645c848f58f6ba56944d5ae62.diff

LOG: [LLVM][CodeGen][SVE] Add isel for zext(setcc(x,0,ne)) -> umin(x,1). (#209452)

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    llvm/test/CodeGen/AArch64/sve-cmp-folds.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 26b0a38f6bae0..9b5c6f9cef125 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -789,6 +789,16 @@ let Predicates = [HasSVE_or_SME] in {
   defm UMAX_ZI   : sve_int_arith_imm1_unsigned<0b01, "umax", AArch64umax_p>;
   defm UMIN_ZI   : sve_int_arith_imm1_unsigned<0b11, "umin", AArch64umin_p>;
 
+  // zext(cmpne(x, splat(0))) -> umin(x, 1)
+  def : Pat<(nxv16i8 (zext (AArch64setcc_z (SVEAllActive), nxv16i8:$LHS, (SVEDup0), SETNE))),
+            (UMIN_ZI_B $LHS, 1)>;
+  def : Pat<(nxv8i16 (zext (AArch64setcc_z (SVEAllActive), nxv8i16:$LHS, (SVEDup0), SETNE))),
+            (UMIN_ZI_H $LHS, 1)>;
+  def : Pat<(nxv4i32 (zext (AArch64setcc_z (SVEAllActive), nxv4i32:$LHS, (SVEDup0), SETNE))),
+            (UMIN_ZI_S $LHS, 1)>;
+  def : Pat<(nxv2i64 (zext (AArch64setcc_z (SVEAllActive), nxv2i64:$LHS, (SVEDup0), SETNE))),
+            (UMIN_ZI_D $LHS, 1)>;
+
   defm MUL_ZI     : sve_int_arith_imm2<"mul", AArch64mul_p>;
   defm MUL_ZPmZ   : sve_int_bin_pred_arit_2<0b000, "mul",   "MUL_ZPZZ",   AArch64mul_m1,         DestructiveBinaryComm>;
   defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh", "SMULH_ZPZZ", int_aarch64_sve_smulh, DestructiveBinaryComm>;

diff  --git a/llvm/test/CodeGen/AArch64/sve-cmp-folds.ll b/llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
index 103e31baa6d41..88b3b3ad2102b 100644
--- a/llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
+++ b/llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
@@ -89,6 +89,46 @@ define <vscale x 2 x i64> @icmp_cnot_nxv2i64(<vscale x 2 x i64> %a) {
   ret <vscale x 2 x i64> %zext
 }
 
+define <vscale x 16 x i8> @icmp_clamp_i1_nxv16i8(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: icmp_clamp_i1_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umin z0.b, z0.b, #1
+; CHECK-NEXT:    ret
+  %mask = icmp ne <vscale x 16 x i8> %a, zeroinitializer
+  %zext = zext <vscale x 16 x i1> %mask to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %zext
+}
+
+define <vscale x 8 x i16> @icmp_clamp_i1_nxv8i16(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: icmp_clamp_i1_nxv8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umin z0.h, z0.h, #1
+; CHECK-NEXT:    ret
+  %mask = icmp ne <vscale x 8 x i16> %a, zeroinitializer
+  %zext = zext <vscale x 8 x i1> %mask to <vscale x 8 x i16>
+  ret <vscale x 8 x i16> %zext
+}
+
+define <vscale x 4 x i32> @icmp_clamp_i1_nxv4i32(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: icmp_clamp_i1_nxv4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umin z0.s, z0.s, #1
+; CHECK-NEXT:    ret
+  %mask = icmp ne <vscale x 4 x i32> %a, zeroinitializer
+  %zext = zext <vscale x 4 x i1> %mask to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %zext
+}
+
+define <vscale x 2 x i64> @icmp_clamp_i1_nxv2i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: icmp_clamp_i1_nxv2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umin z0.d, z0.d, #1
+; CHECK-NEXT:    ret
+  %mask = icmp ne <vscale x 2 x i64> %a, zeroinitializer
+  %zext = zext <vscale x 2 x i1> %mask to <vscale x 2 x i64>
+  ret <vscale x 2 x i64> %zext
+}
+
 define i1 @foo_first(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
 ; CHECK-LABEL: foo_first:
 ; CHECK:       // %bb.0: