[llvm] [LLVM][CodeGen][SVE] Add isel for zext(setcc(x,0,ne)) -> umin(x,1). (PR #209452)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

> Could this benefit fixed length vectors if SVE is available?

I believe so, although the pattern will be different due to type legalisation.  I'll investigate and push up another PR if successful.

https://github.com/llvm/llvm-project/pull/209452