[llvm] [AMDGPU] GCNRewritePartialRegUses - missing superreg (PR #208718)

[Jay Foad via llvm-commits]

jayfoad wrote:

Could you try this instead? 96-bit SGPR subregs have to be 128-bit aligned.
```diff
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de1cae51db1b..b2ce3bb2ff3a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -4304,7 +4304,7 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
                                           unsigned SubReg) const {
   switch (RC->TSFlags & SIRCFlags::RegKindMask) {
   case SIRCFlags::HasSGPR:
-    return std::min(128u, getSubRegIdxSize(SubReg));
+    return std::min(128u, bit_ceil(getSubRegIdxSize(SubReg)));
   case SIRCFlags::HasAGPR:
   case SIRCFlags::HasVGPR:
   case SIRCFlags::HasVGPR | SIRCFlags::HasAGPR:
```

https://github.com/llvm/llvm-project/pull/208718