[llvm] [Gisel] smin/umin optimization rewrites (PR #203939)
Luisa Cicolini via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 14 05:42:34 PDT 2026
https://github.com/luisacicolini updated https://github.com/llvm/llvm-project/pull/203939
>From 76b48cfd1a7deb1d9f8989df0027dac9cb12d110 Mon Sep 17 00:00:00 2001
From: luisacicolini <lc985 at cam.ac.uk>
Date: Mon, 15 Jun 2026 17:13:15 +0100
Subject: [PATCH 01/10] test
---
.../include/llvm/Target/GlobalISel/Combine.td | 26 ++-
.../AArch64/GlobalISel/combine-max-min.mir | 159 ++++++++++++++++++
2 files changed, 184 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index c448a00068006..b12b1afb3d53a 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2173,6 +2173,28 @@ def SubUmaxSub: GICombineRule<
MRI.hasOneNonDBGUse(${max}.getReg()); }]),
(apply (G_SUB $sub1, 0, $A),
(G_UMIN $root, $A, $sub1))>;
+
+// (sub 0, (min X, (sub 0, X))) --> (max X, (sub 0, X))
+def SubSminSub: GICombineRule<
+ (defs root:$root),
+ (match (G_SUB $sub, 0, $A),
+ (G_SMIN $max, $A, $sub),
+ (G_SUB $root, 0, $max),
+ [{ return MRI.hasOneNonDBGUse(${sub}.getReg()) &&
+ MRI.hasOneNonDBGUse(${max}.getReg()); }]),
+ (apply (G_SUB $sub1, 0, $A),
+ (G_SMAX $root, $A, $sub1))>;
+
+// (sub 0, (min X, (sub 0, X))) --> (max X, (sub 0, X))
+def SubUminSub: GICombineRule<
+ (defs root:$root),
+ (match (G_SUB $sub, 0, $A),
+ (G_UMIN $max, $A, $sub),
+ (G_SUB $root, 0, $max),
+ [{ return MRI.hasOneNonDBGUse(${sub}.getReg()) &&
+ MRI.hasOneNonDBGUse(${max}.getReg()); }]),
+ (apply (G_SUB $sub1, 0, $A),
+ (G_UMAX $root, $A, $sub1))>;
def integer_reassoc_combines: GICombineGroup<[
APlusBMinusCMinusB,
@@ -2198,7 +2220,9 @@ def integer_reassoc_combines: GICombineGroup<[
def max_min_combines: GICombineGroup<[
SubSmaxSub,
- SubUmaxSub
+ SubUmaxSub,
+ SubSminSub,
+ SubUminSub
]>;
// fold (A+(shl (0-B), C)) -> (A-(shl B, C))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 4c505f77e1bc4..e3bf013405729 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -156,3 +156,162 @@ body: |
%mul:_(s64) = G_MUL %max, %sub2
$x0 = COPY %mul
RET_ReallyLR implicit $x0
+
+
+...
+---
+name: ASubSMin
+body: |
+ bb.0:
+ liveins: $x0
+
+
+ ; CHECK-LABEL: name: ASubSMin
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s64) = COPY $x0
+ ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %zero, %a
+ ; CHECK-NEXT: %sub2:_(s64) = G_SMAX %a, [[SUB]]
+ ; CHECK-NEXT: $x0 = COPY %sub2(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %zero:_(s64) = G_CONSTANT i64 0
+ %sub1:_(s64) = G_SUB %zero, %a
+ %max:_(s64) = G_SMIN %a, %sub1
+ %sub2:_(s64) = G_SUB %zero, %max
+ $x0 = COPY %sub2
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: ASubSMinVec
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: ASubSMinVec
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: %c:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: %c1:_(<4 x s32>) = G_BUILD_VECTOR %c(s32), %c(s32), %c(s32), %c(s32)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB %c1, %a
+ ; CHECK-NEXT: %sub2:_(<4 x s32>) = G_SMAX %a, [[SUB]]
+ ; CHECK-NEXT: $q0 = COPY %sub2(<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %a:_(<4 x s32>) = COPY $q0
+ %c:_(s32) = G_CONSTANT i32 0
+ %c1:_(<4 x s32>) = G_BUILD_VECTOR %c(s32), %c(s32), %c(s32), %c(s32)
+ %sub1:_(<4 x s32>) = G_SUB %c1, %a
+ %max:_(<4 x s32>) = G_SMIN %a, %sub1
+ %sub2:_(<4 x s32>) = G_SUB %c1, %max
+ $q0 = COPY %sub2
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: ASubSMinOneUse
+body: |
+ bb.0:
+ liveins: $x0
+
+
+ ; CHECK-LABEL: name: ASubSMinOneUse
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s64) = COPY $x0
+ ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %sub1:_(s64) = G_SUB %zero, %a
+ ; CHECK-NEXT: %max:_(s64) = G_SMIN %a, %sub1
+ ; CHECK-NEXT: %sub2:_(s64) = G_SUB %zero, %max
+ ; CHECK-NEXT: %mul:_(s64) = G_MUL %max, %sub2
+ ; CHECK-NEXT: $x0 = COPY %mul(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %zero:_(s64) = G_CONSTANT i64 0
+ %sub1:_(s64) = G_SUB %zero, %a
+ %max:_(s64) = G_SMIN %a, %sub1
+ %sub2:_(s64) = G_SUB %zero, %max
+ %mul:_(s64) = G_MUL %max, %sub2
+ $x0 = COPY %mul
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: ASubUMin
+body: |
+ bb.0:
+ liveins: $x0
+
+
+ ; CHECK-LABEL: name: ASubUMin
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s64) = COPY $x0
+ ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB %zero, %a
+ ; CHECK-NEXT: %sub2:_(s64) = G_UMAX %a, [[SUB]]
+ ; CHECK-NEXT: $x0 = COPY %sub2(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %zero:_(s64) = G_CONSTANT i64 0
+ %sub1:_(s64) = G_SUB %zero, %a
+ %max:_(s64) = G_UMIN %a, %sub1
+ %sub2:_(s64) = G_SUB %zero, %max
+ $x0 = COPY %sub2
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: ASubUMinVec
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; CHECK-LABEL: name: ASubUMinVec
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: %c:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: %c1:_(<4 x s32>) = G_BUILD_VECTOR %c(s32), %c(s32), %c(s32), %c(s32)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB %c1, %a
+ ; CHECK-NEXT: %sub2:_(<4 x s32>) = G_UMAX %a, [[SUB]]
+ ; CHECK-NEXT: $q0 = COPY %sub2(<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %a:_(<4 x s32>) = COPY $q0
+ %c:_(s32) = G_CONSTANT i32 0
+ %c1:_(<4 x s32>) = G_BUILD_VECTOR %c(s32), %c(s32), %c(s32), %c(s32)
+ %sub1:_(<4 x s32>) = G_SUB %c1, %a
+ %max:_(<4 x s32>) = G_UMIN %a, %sub1
+ %sub2:_(<4 x s32>) = G_SUB %c1, %max
+ $q0 = COPY %sub2
+ RET_ReallyLR implicit $q0
+
+...
+---
+name: ASubUMinOneUse
+body: |
+ bb.0:
+ liveins: $x0
+
+
+ ; CHECK-LABEL: name: ASubUMinOneUse
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s64) = COPY $x0
+ ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: %sub1:_(s64) = G_SUB %zero, %a
+ ; CHECK-NEXT: %max:_(s64) = G_UMIN %a, %sub1
+ ; CHECK-NEXT: %sub2:_(s64) = G_SUB %zero, %max
+ ; CHECK-NEXT: %mul:_(s64) = G_MUL %max, %sub2
+ ; CHECK-NEXT: $x0 = COPY %mul(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %zero:_(s64) = G_CONSTANT i64 0
+ %sub1:_(s64) = G_SUB %zero, %a
+ %max:_(s64) = G_UMIN %a, %sub1
+ %sub2:_(s64) = G_SUB %zero, %max
+ %mul:_(s64) = G_MUL %max, %sub2
+ $x0 = COPY %mul
+ RET_ReallyLR implicit $x0
>From 3183a28fe2186c1cec47c642724d7eb0ca30c355 Mon Sep 17 00:00:00 2001
From: luisacicolini <lc985 at cam.ac.uk>
Date: Mon, 15 Jun 2026 17:26:55 +0100
Subject: [PATCH 02/10] other tests
---
.../AArch64/GlobalISel/combine-max-min.ll | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
index c4da01e26c0e6..43380fe76316f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.ll
@@ -85,3 +85,87 @@ define <4 x i32> @ASubUMaxVec(<4 x i32> %a) {
%sub2 = sub <4 x i32> zeroinitializer, %max
ret <4 x i32> %sub2
}
+
+define i64 @ASubSMin(i64 %a) {
+; CHECK-SD-LABEL: ASubSMin:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg x8, x0
+; CHECK-SD-NEXT: cmp x0, x8
+; CHECK-SD-NEXT: cneg x0, x0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ASubSMin:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: neg x8, x0
+; CHECK-GI-NEXT: cmp x0, x8
+; CHECK-GI-NEXT: cneg x0, x0, le
+; CHECK-GI-NEXT: ret
+ %sub1 = sub i64 0, %a
+ %min = call i64 @llvm.smin.i64(i64 %a, i64 %sub1)
+ %sub2 = sub i64 0, %min
+ ret i64 %sub2
+}
+
+; Extra use of %min blocks the combine.
+define i64 @ASubSMinOneUse(i64 %a) {
+; CHECK-LABEL: ASubSMinOneUse:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg x8, x0
+; CHECK-NEXT: cmp x0, x8
+; CHECK-NEXT: cneg x8, x0, ge
+; CHECK-NEXT: mneg x0, x8, x8
+; CHECK-NEXT: ret
+ %sub1 = sub i64 0, %a
+ %min = call i64 @llvm.smin.i64(i64 %a, i64 %sub1)
+ %sub2 = sub i64 0, %min
+ %mul = mul i64 %min, %sub2
+ ret i64 %mul
+}
+
+; 0 - smin(a, 0 - a) -> smax(a, 0 - a) (i.e. -abs(a))
+define <4 x i32> @ASubSMinVec(<4 x i32> %a) {
+; CHECK-LABEL: ASubSMinVec:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v0.4s
+; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %sub1 = sub <4 x i32> zeroinitializer, %a
+ %min = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %sub1)
+ %sub2 = sub <4 x i32> zeroinitializer, %min
+ ret <4 x i32> %sub2
+}
+
+; 0 - umin(a, 0 - a) -> umax(a, 0 - a)
+define i64 @ASubUMin(i64 %a) {
+; CHECK-SD-LABEL: ASubUMin:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: neg x8, x0
+; CHECK-SD-NEXT: cmp x0, x8
+; CHECK-SD-NEXT: cneg x0, x0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ASubUMin:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: neg x8, x0
+; CHECK-GI-NEXT: cmp x0, x8
+; CHECK-GI-NEXT: cneg x0, x0, ls
+; CHECK-GI-NEXT: ret
+ %sub1 = sub i64 0, %a
+ %min = call i64 @llvm.umin.i64(i64 %a, i64 %sub1)
+ %sub2 = sub i64 0, %min
+ ret i64 %sub2
+}
+
+; 0 - umin(a, 0 - a) -> umax(a, 0 - a)
+define <4 x i32> @ASubUMinVec(<4 x i32> %a) {
+; CHECK-LABEL: ASubUMinVec:
+; CHECK: // %bb.0:
+; CHECK-NEXT: neg v1.4s, v0.4s
+; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %sub1 = sub <4 x i32> zeroinitializer, %a
+ %min = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %sub1)
+ %sub2 = sub <4 x i32> zeroinitializer, %min
+ ret <4 x i32> %sub2
+}
+
>From e07ecd7e4cc6de31a683e58ec1527812b03f1bc2 Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Mon, 15 Jun 2026 17:30:16 +0100
Subject: [PATCH 03/10] Apply suggestion from @luisacicolini
---
llvm/include/llvm/Target/GlobalISel/Combine.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index b12b1afb3d53a..385556c2892a3 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2220,7 +2220,7 @@ def integer_reassoc_combines: GICombineGroup<[
def max_min_combines: GICombineGroup<[
SubSmaxSub,
- SubUmaxSub,
+ SubUmaxSub,
SubSminSub,
SubUminSub
]>;
>From 5715b2b7a55e9e65e8d3daf076df5425e7a4ee1d Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 16 Jun 2026 11:34:07 +0100
Subject: [PATCH 04/10] Update llvm/include/llvm/Target/GlobalISel/Combine.td
Co-authored-by: Jay Foad <jay.foad at gmail.com>
---
llvm/include/llvm/Target/GlobalISel/Combine.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 385556c2892a3..7b50cd7f7d647 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2174,8 +2174,8 @@ def SubUmaxSub: GICombineRule<
(apply (G_SUB $sub1, 0, $A),
(G_UMIN $root, $A, $sub1))>;
-// (sub 0, (min X, (sub 0, X))) --> (max X, (sub 0, X))
-def SubSminSub: GICombineRule<
+// (sub 0, (smin X, (sub 0, X))) --> (smax X, (sub 0, X))
+def NegSminNeg: GICombineRule<
(defs root:$root),
(match (G_SUB $sub, 0, $A),
(G_SMIN $max, $A, $sub),
>From 94449c1793bc878222bb69912b505a6a1595997b Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 16 Jun 2026 11:34:15 +0100
Subject: [PATCH 05/10] Update llvm/include/llvm/Target/GlobalISel/Combine.td
Co-authored-by: Jay Foad <jay.foad at gmail.com>
---
llvm/include/llvm/Target/GlobalISel/Combine.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 7b50cd7f7d647..b23372e8e3e2c 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2185,8 +2185,8 @@ def NegSminNeg: GICombineRule<
(apply (G_SUB $sub1, 0, $A),
(G_SMAX $root, $A, $sub1))>;
-// (sub 0, (min X, (sub 0, X))) --> (max X, (sub 0, X))
-def SubUminSub: GICombineRule<
+// (sub 0, (umin X, (sub 0, X))) --> (umax X, (sub 0, X))
+def NegUminNeg: GICombineRule<
(defs root:$root),
(match (G_SUB $sub, 0, $A),
(G_UMIN $max, $A, $sub),
>From 1c4e723a36456f9278ac9a154836cb0ed605251d Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 16 Jun 2026 11:34:43 +0100
Subject: [PATCH 06/10] Apply suggestion from @luisacicolini
---
llvm/include/llvm/Target/GlobalISel/Combine.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index b23372e8e3e2c..f391c5096935a 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -2221,8 +2221,8 @@ def integer_reassoc_combines: GICombineGroup<[
def max_min_combines: GICombineGroup<[
SubSmaxSub,
SubUmaxSub,
- SubSminSub,
- SubUminSub
+ NegSminNeg,
+ NegUminNeg
]>;
// fold (A+(shl (0-B), C)) -> (A-(shl B, C))
>From c58cd73ccfda050b05125bfe357ce226c357a942 Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 14 Jul 2026 13:40:03 +0100
Subject: [PATCH 07/10] Update
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
Co-authored-by: Osman Yasar <osmanyas05 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index e3bf013405729..19500243b1582 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -157,7 +157,6 @@ body: |
$x0 = COPY %mul
RET_ReallyLR implicit $x0
-
...
---
name: ASubSMin
>From 772ca08d6f9cc132983d9109e0637a9a3b3b9939 Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 14 Jul 2026 13:40:12 +0100
Subject: [PATCH 08/10] Update
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
Co-authored-by: Osman Yasar <osmanyas05 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 19500243b1582..01032b1c79148 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -215,7 +215,6 @@ body: |
bb.0:
liveins: $x0
-
; CHECK-LABEL: name: ASubSMinOneUse
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
>From 3ea1935bc87d49190b59d92280c549fc7113adb6 Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 14 Jul 2026 13:40:21 +0100
Subject: [PATCH 09/10] Update
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
Co-authored-by: Osman Yasar <osmanyas05 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 01032b1c79148..974c35fea4e01 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -242,7 +242,6 @@ body: |
bb.0:
liveins: $x0
-
; CHECK-LABEL: name: ASubUMin
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
>From 8ad1eef19cd6a5976a19c203ad26fd99cb52faca Mon Sep 17 00:00:00 2001
From: Luisa Cicolini <48860705+luisacicolini at users.noreply.github.com>
Date: Tue, 14 Jul 2026 13:40:30 +0100
Subject: [PATCH 10/10] Update
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
Co-authored-by: Osman Yasar <osmanyas05 at gmail.com>
---
llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
index 974c35fea4e01..44f066548f969 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-max-min.mir
@@ -292,7 +292,6 @@ body: |
bb.0:
liveins: $x0
-
; CHECK-LABEL: name: ASubUMinOneUse
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
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