[llvm] [AMDGPU] Generalize extractSubregFromImm (PR #208765)

[Jay Foad via llvm-commits]

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@@ -3477,28 +3477,14 @@ void SIInstrInfo::mutateAndCleanupImplicit(MachineInstr &MI,
     MI.removeOperand(I);
 }
 
-std::optional<int64_t> SIInstrInfo::extractSubregFromImm(int64_t Imm,
-                                                         unsigned SubRegIndex) {
-  switch (SubRegIndex) {
-  case AMDGPU::NoSubRegister:
+int64_t SIInstrInfo::extractSubregFromImm(int64_t Imm,
+                                          unsigned SubRegIndex) const {
+  if (SubRegIndex == AMDGPU::NoSubRegister)
     return Imm;
-  case AMDGPU::sub0:
-    return SignExtend64<32>(Imm);
-  case AMDGPU::sub1:
-    return SignExtend64<32>(Imm >> 32);
-  case AMDGPU::lo16:
-    return SignExtend64<16>(Imm);
-  case AMDGPU::hi16:
-    return SignExtend64<16>(Imm >> 16);
-  case AMDGPU::sub1_lo16:
-    return SignExtend64<16>(Imm >> 32);
-  case AMDGPU::sub1_hi16:
-    return SignExtend64<16>(Imm >> 48);
-  default:
-    return std::nullopt;
-  }
-
-  llvm_unreachable("covered subregister switch");
+  assert(RI.getSubRegIdxSize(SubRegIndex) > 0);
+  assert(RI.getSubRegIdxOffset(SubRegIndex) >= 0);
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jayfoad wrote:

> tautological asserts

I was trying to assert that we don't hit the weird cases where they are documented to return -1.

https://github.com/llvm/llvm-project/pull/208765