[llvm] [AMDGPU] merge 16bit mov pairs in post-RA peephole (PR #208625)

[Jay Foad via llvm-commits]

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@@ -763,6 +766,229 @@ MachineInstrBuilder SIPreEmitPeephole::createUnpackedMI(MachineInstr &I,
   return NewMI;
 }
 
+// Helper: extract the src operand and whether it is from the hi16 half.
+// Post-RA, both V_MOV_B16_t16_e32 and V_MOV_B16_t16_e64 use VGPR_16 physical
+// registers whose encoding already encodes hi/lo (IS_HI16 bit).
+// Returns false if the source is not a physical VGPR_16 or immediate zero.
+//
+// Operand layouts (post-RA, physical registers):
+//   V_MOV_B16_t16_e32: dst(0), src0(1)
+//   V_MOV_B16_t16_e64: dst(0), src0_mods(1), src0(2), op_sel(3)
+static bool getMovB16Info(const MachineInstr &MI, const SIRegisterInfo *TRI,
+                          MCRegister &SrcReg16, MCRegister &SrcReg32,
+                          bool &SrcIsHi, bool &SrcIsImm, int64_t &ImmVal) {
+  SrcIsImm = false;
+  SrcIsHi = false;
+  SrcReg16 = MCRegister();
+  SrcReg32 = MCRegister();
+
+  unsigned Opc = MI.getOpcode();
+  const MachineOperand *SrcOp = nullptr;
+
+  if (Opc == AMDGPU::V_MOV_B16_t16_e64)
+    SrcOp = &MI.getOperand(2);
+  else if (Opc == AMDGPU::V_MOV_B16_t16_e32)
+    SrcOp = &MI.getOperand(1);
+  else
+    return false;
+
+  if (SrcOp->isImm()) {
+    SrcIsImm = true;
+    ImmVal = SrcOp->getImm();
+    return true;
+  }
+
+  if (!SrcOp->isReg() || !SrcOp->getReg().isPhysical())
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jayfoad wrote:

Do these checks ever fail?

https://github.com/llvm/llvm-project/pull/208625