[llvm] [AArch64] Lower fixed width bf16 fpround (PR #209411)

[Paul Walker via llvm-commits]

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@@ -27405,11 +27362,12 @@ static SDValue performSTORECombine(SDNode *N,
   // We purposefully don't care about legality of the nodes here as we know
   // they can be split down into something legal.
   if (DCI.isBeforeLegalizeOps() && Value.getOpcode() == ISD::FP_ROUND &&
-      Value.getNode()->hasOneUse() && ST->isUnindexed() &&
+      Value->hasOneUse() && ST->isUnindexed() &&
       Subtarget->useSVEForFixedLengthVectors() &&
       ValueVT.isFixedLengthVector() &&
       ValueVT.getFixedSizeInBits() >= Subtarget->getMinSVEVectorSizeInBits() &&
-      hasValidElementTypeForFPTruncStore(Value.getOperand(0).getValueType()))
+      hasValidElementTypeForFPTruncStore(Value.getOperand(0).getValueType()) &&
+      Value.getValueType().getScalarType() != MVT::bf16)
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paulwalker-arm wrote:

Given the rational for `hasValidElementTypeForFPTruncStore` it makes sense for it to take both the pre and post trunc types now the latter is relevant.

https://github.com/llvm/llvm-project/pull/209411