[llvm] [RISCV][P-ext] Add packed saturating rounding shift codegen (PR #208630)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 14 02:58:51 PDT 2026
https://github.com/sihuan updated https://github.com/llvm/llvm-project/pull/208630
>From 999f3676f448aac5ced8158b6b65ae1c51d56ffb Mon Sep 17 00:00:00 2001
From: SiHuaN <liyongtai at iscas.ac.cn>
Date: Thu, 9 Jul 2026 10:36:02 +0000
Subject: [PATCH 1/3] [RISCV][P-ext] Add packed saturating rounding shift
codegen
---
llvm/include/llvm/IR/IntrinsicsRISCV.td | 10 ++
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 48 +++++++
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 15 ++
llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 45 +++++-
llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 151 +++++++++++++++++---
5 files changed, 246 insertions(+), 23 deletions(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 28cde8111241c..fca28455f2117 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -2061,6 +2061,16 @@ class RVPBinaryIntrinsic
def int_riscv_pabd : RVPBinaryIntrinsic;
def int_riscv_pabdu : RVPBinaryIntrinsic;
+ // Packed Saturating and Rounding Shifts.
+ class RVPShiftIntrinsic
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_i32_ty],
+ [IntrNoMem, IntrSpeculatable]>;
+ def int_riscv_pssha : RVPShiftIntrinsic;
+ def int_riscv_psshar : RVPShiftIntrinsic;
+ def int_riscv_psshl : RVPShiftIntrinsic;
+ def int_riscv_psshlr : RVPShiftIntrinsic;
+
// Packed Exchanged Addition and Subtraction.
def int_riscv_pas : RVPBinaryIntrinsic;
def int_riscv_psa : RVPBinaryIntrinsic;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index fda994a04b00f..57f8d164db248 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11752,6 +11752,22 @@ static inline bool isValidEGW(int EGS, EVT VT,
EGS * VT.getScalarSizeInBits();
}
+static unsigned getRVPShiftOpcode(Intrinsic::ID IntNo) {
+ switch (IntNo) {
+ default:
+ llvm_unreachable(
+ "Unexpected RISC-V packed saturating and rounding shift intrinsic");
+ case Intrinsic::riscv_pssha:
+ return RISCVISD::PSSHA;
+ case Intrinsic::riscv_psshar:
+ return RISCVISD::PSSHAR;
+ case Intrinsic::riscv_psshl:
+ return RISCVISD::PSSHL;
+ case Intrinsic::riscv_psshlr:
+ return RISCVISD::PSSHLR;
+ }
+}
+
SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
unsigned IntNo = Op.getConstantOperandVal(0);
@@ -11920,6 +11936,18 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getNode(Opc, DL, Op.getValueType(), Op.getOperand(1),
Op.getOperand(2));
}
+ case Intrinsic::riscv_pssha:
+ case Intrinsic::riscv_psshar:
+ case Intrinsic::riscv_psshl:
+ case Intrinsic::riscv_psshlr: {
+ SDValue ShAmt = Op.getOperand(2);
+ if (ShAmt.getValueType().bitsLT(XLenVT))
+ ShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, ShAmt);
+ else if (ShAmt.getValueType().bitsGT(XLenVT))
+ ShAmt = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, ShAmt);
+ return DAG.getNode(getRVPShiftOpcode(IntNo), DL, Op.getValueType(),
+ Op.getOperand(1), ShAmt);
+ }
case Intrinsic::riscv_pabdsumu:
case Intrinsic::riscv_pabdsumau: {
// On RV32 an i32-result absolute difference sum over a 64-bit (GPRPair)
@@ -16000,6 +16028,26 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
DAG.getVectorIdxConstant(0, DL)));
return;
}
+ case Intrinsic::riscv_pssha:
+ case Intrinsic::riscv_psshar:
+ case Intrinsic::riscv_psshl:
+ case Intrinsic::riscv_psshlr: {
+ MVT VT = N->getSimpleValueType(0);
+ if (!Subtarget.is64Bit() || VT != MVT::v2i16)
+ return;
+
+ MVT WideVT = MVT::v4i16;
+ SDValue Op0 = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT,
+ N->getOperand(1), DAG.getUNDEF(VT));
+ SDValue ShAmt = N->getOperand(2);
+ if (ShAmt.getValueType().bitsLT(Subtarget.getXLenVT()))
+ ShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), ShAmt);
+ SDValue Res =
+ DAG.getNode(getRVPShiftOpcode(IntNo), DL, WideVT, Op0, ShAmt);
+ Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
+ DAG.getVectorIdxConstant(0, DL)));
+ return;
+ }
case Intrinsic::riscv_predsum:
case Intrinsic::riscv_predsumu: {
bool IsSigned = IntNo == Intrinsic::riscv_predsum;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 7fa7c96ca99ca..3da9eb78e8d47 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1882,6 +1882,9 @@ def riscv_pshl : RVSDNode<"PSHL", SDT_RISCVPackedShift>;
def riscv_psrl : RVSDNode<"PSRL", SDT_RISCVPackedShift>;
def riscv_psra : RVSDNode<"PSRA", SDT_RISCVPackedShift>;
def riscv_pssha : RVSDNode<"PSSHA", SDT_RISCVPackedShift>;
+def riscv_psshar : RVSDNode<"PSSHAR", SDT_RISCVPackedShift>;
+def riscv_psshl : RVSDNode<"PSSHL", SDT_RISCVPackedShift>;
+def riscv_psshlr : RVSDNode<"PSSHLR", SDT_RISCVPackedShift>;
// The immediate for these is the number of trailing ones in the max value.
def riscv_sati : RVSDNode<"SATI", SDTIntBinOp>;
@@ -2093,6 +2096,9 @@ let Predicates = [HasStdExtP] in {
// 16-bit signed saturation shift left patterns
def : PatGprImm<riscv_pssha, PSSLAI_H, uimm4, XLenVecI16VT>;
def : PatGprShift<riscv_pssha, PSSHA_HS, XLenVecI16VT>;
+ def : PatGprShift<riscv_psshar, PSSHAR_HS, XLenVecI16VT>;
+ def : PatGprShift<riscv_psshl, PSSHL_HS, XLenVecI16VT>;
+ def : PatGprShift<riscv_psshlr, PSSHLR_HS, XLenVecI16VT>;
// 8-bit logical shift left/right
def : PatGprShiftMask<riscv_pshl, PSLL_BS, shiftMask8, XLenVecI8VT>;
@@ -2414,10 +2420,16 @@ let append Predicates = [IsRV32] in {
// 16-bit signed saturation shift left patterns
def : PatGprPairImm<riscv_pssha, PSSLAI_DH, uimm4, v4i16>;
def : PatGprPairShift<riscv_pssha, PSSHA_DHS, v4i16>;
+ def : PatGprPairShift<riscv_psshar, PSSHAR_DHS, v4i16>;
+ def : PatGprPairShift<riscv_psshl, PSSHL_DHS, v4i16>;
+ def : PatGprPairShift<riscv_psshlr, PSSHLR_DHS, v4i16>;
// 32-bit signed saturation shift left patterns
def : PatGprPairImm<riscv_pssha, PSSLAI_DW, uimm5, v2i32>;
def : PatGprPairShift<riscv_pssha, PSSHA_DWS, v2i32>;
+ def : PatGprPairShift<riscv_psshar, PSSHAR_DWS, v2i32>;
+ def : PatGprPairShift<riscv_psshl, PSSHL_DWS, v2i32>;
+ def : PatGprPairShift<riscv_psshlr, PSSHLR_DWS, v2i32>;
// 8-bit logical shift left/right
def : PatGprPairShiftMask<riscv_pshl, PSLL_DBS, shiftMask8, v8i8>;
@@ -2666,6 +2678,9 @@ let append Predicates = [IsRV64] in {
// 32-bit signed saturation shift left patterns
def : PatGprImm<riscv_pssha, PSSLAI_W, uimm5, v2i32>;
def : PatGprShift<riscv_pssha, PSSHA_WS, v2i32>;
+ def : PatGprShift<riscv_psshar, PSSHAR_WS, v2i32>;
+ def : PatGprShift<riscv_psshl, PSSHL_WS, v2i32>;
+ def : PatGprShift<riscv_psshlr, PSSHLR_WS, v2i32>;
// 32-bit logical shift left/right
def : PatGprShiftMask<riscv_pshl, PSLL_WS, shiftMask32, v2i32>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 48c7b3b14847e..8595751b2dcd3 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -1251,6 +1251,43 @@ define <4 x i8> @test_psra_bs_vec_shamt(<4 x i8> %a, <4 x i8> %b) {
ret <4 x i8> %res
}
+; Packed saturating and rounding shifts
+define <2 x i16> @test_pssha_s_i16x2(<2 x i16> %a, i32 %shamt) {
+; CHECK-LABEL: test_pssha_s_i16x2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pssha.hs a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pssha.v2i16.i32(<2 x i16> %a, i32 %shamt)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_psshar_s_i16x2(<2 x i16> %a, i32 %shamt) {
+; CHECK-LABEL: test_psshar_s_i16x2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psshar.hs a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.psshar.v2i16.i32(<2 x i16> %a, i32 %shamt)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_psshl_s_u16x2(<2 x i16> %a, i32 %shamt) {
+; CHECK-LABEL: test_psshl_s_u16x2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psshl.hs a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.psshl.v2i16.i32(<2 x i16> %a, i32 %shamt)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_psshlr_s_u16x2(<2 x i16> %a, i32 %shamt) {
+; CHECK-LABEL: test_psshlr_s_u16x2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psshlr.hs a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.psshlr.v2i16.i32(<2 x i16> %a, i32 %shamt)
+ ret <2 x i16> %res
+}
+
; Test packed multiply high signed for v4i8
define <4 x i8> @test_pmulh_b(<4 x i8> %a, <4 x i8> %b) {
; RV32-LABEL: test_pmulh_b:
@@ -2219,10 +2256,10 @@ define <2 x i16> @test_select_v2i16(i1 %cond, <2 x i16> %a, <2 x i16> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB154_2
+; CHECK-NEXT: bnez a3, .LBB158_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB154_2:
+; CHECK-NEXT: .LBB158_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %res
@@ -2233,10 +2270,10 @@ define <4 x i8> @test_select_v4i8(i1 %cond, <4 x i8> %a, <4 x i8> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a3, a0, 1
; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: bnez a3, .LBB155_2
+; CHECK-NEXT: bnez a3, .LBB159_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: .LBB155_2:
+; CHECK-NEXT: .LBB159_2:
; CHECK-NEXT: ret
%res = select i1 %cond, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %res
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 9cbd64717c1d5..33187187223ed 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -2296,6 +2296,119 @@ define <2 x i32> @test_psra_ws_vec_shamt(<2 x i32> %a, <2 x i32> %b) {
ret <2 x i32> %res
}
+; Packed saturating and rounding shifts
+define <4 x i16> @test_pssha_s_i16x4(<4 x i16> %a, i32 %shamt) {
+; RV32-LABEL: test_pssha_s_i16x4:
+; RV32: # %bb.0:
+; RV32-NEXT: pssha.dhs a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssha_s_i16x4:
+; RV64: # %bb.0:
+; RV64-NEXT: pssha.hs a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pssha.v4i16.i32(<4 x i16> %a, i32 %shamt)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_pssha_s_i32x2(<2 x i32> %a, i32 %shamt) {
+; RV32-LABEL: test_pssha_s_i32x2:
+; RV32: # %bb.0:
+; RV32-NEXT: pssha.dws a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pssha_s_i32x2:
+; RV64: # %bb.0:
+; RV64-NEXT: pssha.ws a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pssha.v2i32.i32(<2 x i32> %a, i32 %shamt)
+ ret <2 x i32> %res
+}
+
+define <4 x i16> @test_psshar_s_i16x4(<4 x i16> %a, i32 %shamt) {
+; RV32-LABEL: test_psshar_s_i16x4:
+; RV32: # %bb.0:
+; RV32-NEXT: psshar.dhs a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshar_s_i16x4:
+; RV64: # %bb.0:
+; RV64-NEXT: psshar.hs a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.psshar.v4i16.i32(<4 x i16> %a, i32 %shamt)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_psshar_s_i32x2(<2 x i32> %a, i32 %shamt) {
+; RV32-LABEL: test_psshar_s_i32x2:
+; RV32: # %bb.0:
+; RV32-NEXT: psshar.dws a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshar_s_i32x2:
+; RV64: # %bb.0:
+; RV64-NEXT: psshar.ws a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.psshar.v2i32.i32(<2 x i32> %a, i32 %shamt)
+ ret <2 x i32> %res
+}
+
+define <4 x i16> @test_psshl_s_u16x4(<4 x i16> %a, i32 %shamt) {
+; RV32-LABEL: test_psshl_s_u16x4:
+; RV32: # %bb.0:
+; RV32-NEXT: psshl.dhs a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshl_s_u16x4:
+; RV64: # %bb.0:
+; RV64-NEXT: psshl.hs a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.psshl.v4i16.i32(<4 x i16> %a, i32 %shamt)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_psshl_s_u32x2(<2 x i32> %a, i32 %shamt) {
+; RV32-LABEL: test_psshl_s_u32x2:
+; RV32: # %bb.0:
+; RV32-NEXT: psshl.dws a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshl_s_u32x2:
+; RV64: # %bb.0:
+; RV64-NEXT: psshl.ws a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.psshl.v2i32.i32(<2 x i32> %a, i32 %shamt)
+ ret <2 x i32> %res
+}
+
+define <4 x i16> @test_psshlr_s_u16x4(<4 x i16> %a, i32 %shamt) {
+; RV32-LABEL: test_psshlr_s_u16x4:
+; RV32: # %bb.0:
+; RV32-NEXT: psshlr.dhs a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshlr_s_u16x4:
+; RV64: # %bb.0:
+; RV64-NEXT: psshlr.hs a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.psshlr.v4i16.i32(<4 x i16> %a, i32 %shamt)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_psshlr_s_u32x2(<2 x i32> %a, i32 %shamt) {
+; RV32-LABEL: test_psshlr_s_u32x2:
+; RV32: # %bb.0:
+; RV32-NEXT: psshlr.dws a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_psshlr_s_u32x2:
+; RV64: # %bb.0:
+; RV64-NEXT: psshlr.ws a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.psshlr.v2i32.i32(<2 x i32> %a, i32 %shamt)
+ ret <2 x i32> %res
+}
+
; Test packed multiply high signed
define <8 x i8> @test_pmulh_b(<8 x i8> %a, <8 x i8> %b) {
; RV32-LABEL: test_pmulh_b:
@@ -4443,12 +4556,12 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; RV32-LABEL: test_select_v4i16:
; RV32: # %bb.0:
; RV32-NEXT: andi a5, a0, 1
-; RV32-NEXT: bnez a5, .LBB228_2
+; RV32-NEXT: bnez a5, .LBB236_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a3
; RV32-NEXT: mv a1, a4
; RV32-NEXT: ret
-; RV32-NEXT: .LBB228_2:
+; RV32-NEXT: .LBB236_2:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
@@ -4457,10 +4570,10 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) {
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: bnez a3, .LBB228_2
+; RV64-NEXT: bnez a3, .LBB236_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a2
-; RV64-NEXT: .LBB228_2:
+; RV64-NEXT: .LBB236_2:
; RV64-NEXT: ret
%res = select i1 %cond, <4 x i16> %a, <4 x i16> %b
ret <4 x i16> %res
@@ -4470,12 +4583,12 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; RV32-LABEL: test_select_v8i8:
; RV32: # %bb.0:
; RV32-NEXT: andi a5, a0, 1
-; RV32-NEXT: bnez a5, .LBB229_2
+; RV32-NEXT: bnez a5, .LBB237_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a3
; RV32-NEXT: mv a1, a4
; RV32-NEXT: ret
-; RV32-NEXT: .LBB229_2:
+; RV32-NEXT: .LBB237_2:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
@@ -4484,10 +4597,10 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) {
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: bnez a3, .LBB229_2
+; RV64-NEXT: bnez a3, .LBB237_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a2
-; RV64-NEXT: .LBB229_2:
+; RV64-NEXT: .LBB237_2:
; RV64-NEXT: ret
%res = select i1 %cond, <8 x i8> %a, <8 x i8> %b
ret <8 x i8> %res
@@ -4497,12 +4610,12 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; RV32-LABEL: test_select_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: andi a5, a0, 1
-; RV32-NEXT: bnez a5, .LBB230_2
+; RV32-NEXT: bnez a5, .LBB238_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a3
; RV32-NEXT: mv a1, a4
; RV32-NEXT: ret
-; RV32-NEXT: .LBB230_2:
+; RV32-NEXT: .LBB238_2:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: ret
@@ -4511,10 +4624,10 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) {
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
; RV64-NEXT: mv a0, a1
-; RV64-NEXT: bnez a3, .LBB230_2
+; RV64-NEXT: bnez a3, .LBB238_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a2
-; RV64-NEXT: .LBB230_2:
+; RV64-NEXT: .LBB238_2:
; RV64-NEXT: ret
%res = select i1 %cond, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %res
@@ -4562,16 +4675,16 @@ define <2 x i32> @test_vselect_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; RV32: # %bb.0:
; RV32-NEXT: pmslt.dw a6, a2, a0
; RV32-NEXT: mv a0, a4
-; RV32-NEXT: beqz a7, .LBB233_3
+; RV32-NEXT: beqz a7, .LBB241_3
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: beqz a6, .LBB233_4
-; RV32-NEXT: .LBB233_2:
+; RV32-NEXT: beqz a6, .LBB241_4
+; RV32-NEXT: .LBB241_2:
; RV32-NEXT: mv a1, a5
; RV32-NEXT: ret
-; RV32-NEXT: .LBB233_3:
+; RV32-NEXT: .LBB241_3:
; RV32-NEXT: mv a5, a3
-; RV32-NEXT: bnez a6, .LBB233_2
-; RV32-NEXT: .LBB233_4:
+; RV32-NEXT: bnez a6, .LBB241_2
+; RV32-NEXT: .LBB241_4:
; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a5
; RV32-NEXT: ret
@@ -5845,4 +5958,4 @@ define <4 x i16> @test_psabs_v4i16(<4 x i16> %a) {
; RV64-NEXT: ret
%res = call <4 x i16> @llvm.riscv.psabs.v4i16(<4 x i16> %a)
ret <4 x i16> %res
-}
\ No newline at end of file
+}
>From 0a8209c6ed8e0f02e64c5a79269886a581e9584b Mon Sep 17 00:00:00 2001
From: SiHuaN <liyongtai at iscas.ac.cn>
Date: Mon, 13 Jul 2026 14:44:34 +0000
Subject: [PATCH 2/3] [RISCV][P-ext] Use getAnyExtOrTrunc for packed shifts
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 57f8d164db248..efb6852674a89 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11941,10 +11941,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::riscv_psshl:
case Intrinsic::riscv_psshlr: {
SDValue ShAmt = Op.getOperand(2);
- if (ShAmt.getValueType().bitsLT(XLenVT))
- ShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, ShAmt);
- else if (ShAmt.getValueType().bitsGT(XLenVT))
- ShAmt = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, ShAmt);
+ ShAmt = DAG.getAnyExtOrTrunc(ShAmt, DL, XLenVT);
return DAG.getNode(getRVPShiftOpcode(IntNo), DL, Op.getValueType(),
Op.getOperand(1), ShAmt);
}
@@ -16040,8 +16037,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
SDValue Op0 = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT,
N->getOperand(1), DAG.getUNDEF(VT));
SDValue ShAmt = N->getOperand(2);
- if (ShAmt.getValueType().bitsLT(Subtarget.getXLenVT()))
- ShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), ShAmt);
+ ShAmt = DAG.getAnyExtOrTrunc(ShAmt, DL, Subtarget.getXLenVT());
SDValue Res =
DAG.getNode(getRVPShiftOpcode(IntNo), DL, WideVT, Op0, ShAmt);
Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
>From 3c0d5d96e89b4ffbf13f5249d55b5390353868db Mon Sep 17 00:00:00 2001
From: SiHuaN <liyongtai at iscas.ac.cn>
Date: Tue, 14 Jul 2026 09:47:18 +0000
Subject: [PATCH 3/3] [RISCV][P-ext] Use getExtractSubvector for packed shifts
Address review comment: use DAG.getExtractSubvector helper instead of
constructing the ISD::EXTRACT_SUBVECTOR node manually.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index efb6852674a89..124808c6b8400 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16040,8 +16040,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
ShAmt = DAG.getAnyExtOrTrunc(ShAmt, DL, Subtarget.getXLenVT());
SDValue Res =
DAG.getNode(getRVPShiftOpcode(IntNo), DL, WideVT, Op0, ShAmt);
- Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
- DAG.getVectorIdxConstant(0, DL)));
+ Results.push_back(DAG.getExtractSubvector(DL, VT, Res, 0));
return;
}
case Intrinsic::riscv_predsum:
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