[llvm] [AMDGPU] Allow SCC-only implicit defs and mark SOP2 SALU as rematerializable (PR #187084)

[Jay Foad via llvm-commits]

================
@@ -197,6 +198,14 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
     return false;
   }
 
+  /// Returns true if this instruction can be safely rematerialized at UseIdx
+  /// even if it has implicit physical register defs that are live.
+  virtual bool isImplicitDefRematerializableAt(const MachineInstr &MI,
+                                               SlotIndex UseIdx,
+                                               LiveIntervals &LIS) const {
+    return true;
----------------
jayfoad wrote:

Wouldn't it make more sense for the default implementation to check whether any implicitly defined physical registers are live at the remat point (like you're currently doing for SCC in SIInstrInfo::isImplicitDefRematerializableAt) and then the X86 implementation can override it to ignore certain registers where it has a target-specific way to remat without clobbering them?

https://github.com/llvm/llvm-project/pull/187084