[llvm] [GlobalISel] Fix crash in isConstantOrConstantSplatVectorFP for non-r… (PR #208657)
Mateusz Chudyk via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 14 02:42:13 PDT 2026
https://github.com/mateuszchudyk updated https://github.com/llvm/llvm-project/pull/208657
>From ca17262aa51850257d1e115ea25fe5ccfa4be64e Mon Sep 17 00:00:00 2001
From: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: Wed, 8 Jul 2026 17:55:56 +0200
Subject: [PATCH 1/4] [GlobalISel] Fix crash in
isConstantOrConstantSplatVectorFP for non-register operands
isConstantOrConstantSplatVectorFP unconditionally accessed operand 0
as a register, which causes a crash when the instruction is INLINEASM
(whose operand 0 is the asm string, not a register def).
This can happen when matchRepeatedFPDivisor walks the use-def chain
of a G_FDIV operand and reaches an INLINEASM instruction that defines
the dividend.
Add an early return if operand 0 is not a register.
---
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 2 ++
.../combine-fdiv-inlineasm-operand.mir | 27 +++++++++++++++++++
2 files changed, 29 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index fbb54d8971502..b65fb8451ccf9 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -1542,6 +1542,8 @@ llvm::isConstantOrConstantSplatVector(MachineInstr &MI,
std::optional<APFloat>
llvm::isConstantOrConstantSplatVectorFP(MachineInstr &MI,
const MachineRegisterInfo &MRI) {
+ if (!MI.getOperand(0).isReg())
+ return std::nullopt;
Register Def = MI.getOperand(0).getReg();
if (auto FpConst = getFConstantVRegValWithLookThrough(Def, MRI))
return FpConst->Value;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
new file mode 100644
index 0000000000000..72aeb27612add
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
@@ -0,0 +1,27 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner %s | FileCheck %s
+
+---
+name: fdiv_inlineasm_numerator
+alignment: 4
+legalized: false
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; Regression test for isConstantOrConstantSplatVectorFP.
+ ; When G_FDIV's numerator is defined by INLINEASM, the combiner must not
+ ; crash by assuming operand 0 of the defining instruction is a register.
+ ; CHECK-LABEL: name: fdiv_inlineasm_numerator
+ ; CHECK: %y:_(s32) = G_FCONSTANT float 2.000000e+00
+ ; CHECK-NEXT: INLINEASM &"fmov $0, #1.0", sideeffect attdialect, regdef:FPR32, def %x(s32)
+ ; CHECK-NEXT: %div:_(s32) = arcp G_FDIV %x, %y
+ ; CHECK-NEXT: $s0 = COPY %div(s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ %y:_(s32) = G_FCONSTANT float 2.0
+ INLINEASM &"fmov $0, #1.0", sideeffect attdialect, regdef:FPR32, def %x:fpr32(s32)
+ %div:_(s32) = arcp G_FDIV %x:fpr32(s32), %y:_(s32)
+ $s0 = COPY %div(s32)
+ RET_ReallyLR implicit $s0
+...
>From dc4f6a650428cc90f63485868f86145483d97045 Mon Sep 17 00:00:00 2001
From: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: Tue, 14 Jul 2026 09:59:41 +0200
Subject: [PATCH 2/4] update test
---
.../combine-fdiv-inlineasm-operand.mir | 39 +++++++++----------
1 file changed, 18 insertions(+), 21 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
index 72aeb27612add..60ccd4c429ffe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-fdiv-inlineasm-operand.mir
@@ -2,26 +2,23 @@
# RUN: llc -o - -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner %s | FileCheck %s
---
-name: fdiv_inlineasm_numerator
-alignment: 4
-legalized: false
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
+name: fdiv_inlineasm_as_numerator
body: |
- bb.0:
- ; Regression test for isConstantOrConstantSplatVectorFP.
- ; When G_FDIV's numerator is defined by INLINEASM, the combiner must not
- ; crash by assuming operand 0 of the defining instruction is a register.
- ; CHECK-LABEL: name: fdiv_inlineasm_numerator
- ; CHECK: %y:_(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK-NEXT: INLINEASM &"fmov $0, #1.0", sideeffect attdialect, regdef:FPR32, def %x(s32)
- ; CHECK-NEXT: %div:_(s32) = arcp G_FDIV %x, %y
- ; CHECK-NEXT: $s0 = COPY %div(s32)
- ; CHECK-NEXT: RET_ReallyLR implicit $s0
- %y:_(s32) = G_FCONSTANT float 2.0
- INLINEASM &"fmov $0, #1.0", sideeffect attdialect, regdef:FPR32, def %x:fpr32(s32)
- %div:_(s32) = arcp G_FDIV %x:fpr32(s32), %y:_(s32)
- $s0 = COPY %div(s32)
- RET_ReallyLR implicit $s0
+ bb.1:
+ liveins: $x0
+ ; CHECK-LABEL: name: fdiv_inlineasm_as_numerator
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 2.000000e+00
+ ; CHECK-NEXT: INLINEASM &"fmov $0, #1.0", sideeffect attdialect, regdef:FPR32, def %1(f32)
+ ; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(f32) = arcp G_FDIV %1, [[C]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: G_STORE [[FDIV]](f32), [[COPY]](p0) :: (store (f32))
+ ; CHECK-NEXT: RET_ReallyLR
+ %0:_(f32) = G_FCONSTANT float 2.0
+ INLINEASM &"fmov $0, #1.0", sideeffect attdialect, regdef:FPR32, def %1:fpr32(f32)
+ %2:_(f32) = arcp G_FDIV %1:fpr32(f32), %0:_(f32)
+ %3:_(p0) = COPY $x0
+ G_STORE %2(f32), %3(p0) :: (store (f32))
+ RET_ReallyLR
...
>From 06f569806fed4f3e071a4c2f295febb651afaf2f Mon Sep 17 00:00:00 2001
From: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: Tue, 14 Jul 2026 11:12:19 +0200
Subject: [PATCH 3/4] Change API of isConstantOrConstantSplatVectorFP
---
llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 5 +-
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 2 +-
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 5 +-
.../Target/AMDGPU/AMDGPUCombinerHelper.cpp | 8 +--
.../CodeGen/GlobalISel/GISelUtilsTest.cpp | 54 +++++++++----------
5 files changed, 33 insertions(+), 41 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index 93fc33a61eb06..48e865960cc65 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -552,12 +552,11 @@ LLVM_ABI std::optional<APInt>
isConstantOrConstantSplatVector(MachineInstr &MI,
const MachineRegisterInfo &MRI);
-/// Determines if \p MI defines a float constant integer or a splat vector of
+/// Determines if \p Def defines a float constant integer or a splat vector of
/// float constant integers.
/// \returns the float constant or std::nullopt.
LLVM_ABI std::optional<APFloat>
-isConstantOrConstantSplatVectorFP(MachineInstr &MI,
- const MachineRegisterInfo &MRI);
+isConstantOrConstantSplatVectorFP(Register Def, const MachineRegisterInfo &MRI);
/// Attempt to match a unary predicate against a scalar/splat constant or every
/// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 072f194b36d5a..dc5de81c682a0 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -7037,7 +7037,7 @@ bool CombinerHelper::matchRepeatedFPDivisor(
return false;
auto IsOne = [this](Register X) {
- auto N0CFP = isConstantOrConstantSplatVectorFP(*MRI.getVRegDef(X), MRI);
+ auto N0CFP = isConstantOrConstantSplatVectorFP(X, MRI);
return N0CFP && (N0CFP->isOne() || N0CFP->isMinusOne());
};
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index b65fb8451ccf9..4ccb7d0e5dd7f 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -1540,11 +1540,8 @@ llvm::isConstantOrConstantSplatVector(MachineInstr &MI,
}
std::optional<APFloat>
-llvm::isConstantOrConstantSplatVectorFP(MachineInstr &MI,
+llvm::isConstantOrConstantSplatVectorFP(Register Def,
const MachineRegisterInfo &MRI) {
- if (!MI.getOperand(0).isReg())
- return std::nullopt;
- Register Def = MI.getOperand(0).getReg();
if (auto FpConst = getFConstantVRegValWithLookThrough(Def, MRI))
return FpConst->Value;
auto MaybeCstFP = getFConstantSplat(Def, MRI, /*allowUndef=*/false);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
index 955c561f9052c..a75c093a9e7ff 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
@@ -493,15 +493,15 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(
return false;
Register SelectCondReg = Sel.getOperand(1).getReg();
- MachineInstr *SelectTrue = MRI.getVRegDef(Sel.getOperand(2).getReg());
- MachineInstr *SelectFalse = MRI.getVRegDef(Sel.getOperand(3).getReg());
+ Register SelectTrueReg = Sel.getOperand(2).getReg();
+ Register SelectFalseReg = Sel.getOperand(3).getReg();
const auto SelectTrueVal =
- isConstantOrConstantSplatVectorFP(*SelectTrue, MRI);
+ isConstantOrConstantSplatVectorFP(SelectTrueReg, MRI);
if (!SelectTrueVal)
return false;
const auto SelectFalseVal =
- isConstantOrConstantSplatVectorFP(*SelectFalse, MRI);
+ isConstantOrConstantSplatVectorFP(SelectFalseReg, MRI);
if (!SelectFalseVal)
return false;
diff --git a/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp b/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
index 9163663c2b776..1131395590615 100644
--- a/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
@@ -451,56 +451,52 @@ TEST_F(AMDGPUGISelMITest, isConstantOrConstantSplatVectorFP) {
collectNonCopyMI(MIList, MF);
- EXPECT_TRUE(isConstantOrConstantSplatVectorFP(*MIList[0], *MRI).has_value());
- auto val = isConstantOrConstantSplatVectorFP(*MIList[0], *MRI).value();
+ auto GetReg = [&](int I) { return MIList[I]->getOperand(0).getReg(); };
+
+ EXPECT_TRUE(isConstantOrConstantSplatVectorFP(GetReg(0), *MRI).has_value());
+ auto val = isConstantOrConstantSplatVectorFP(GetReg(0), *MRI).value();
EXPECT_EQ(2.0, val.convertToFloat());
- EXPECT_TRUE(isConstantOrConstantSplatVectorFP(*MIList[1], *MRI).has_value());
- val = isConstantOrConstantSplatVectorFP(*MIList[1], *MRI).value();
+ EXPECT_TRUE(isConstantOrConstantSplatVectorFP(GetReg(1), *MRI).has_value());
+ val = isConstantOrConstantSplatVectorFP(GetReg(1), *MRI).value();
EXPECT_EQ(0.0, val.convertToFloat());
- EXPECT_TRUE(isConstantOrConstantSplatVectorFP(*MIList[2], *MRI).has_value());
- val = isConstantOrConstantSplatVectorFP(*MIList[2], *MRI).value();
+ EXPECT_TRUE(isConstantOrConstantSplatVectorFP(GetReg(2), *MRI).has_value());
+ val = isConstantOrConstantSplatVectorFP(GetReg(2), *MRI).value();
EXPECT_EQ(0.03, val.convertToDouble());
- EXPECT_FALSE(isConstantOrConstantSplatVectorFP(*MIList[3], *MRI).has_value());
+ EXPECT_FALSE(isConstantOrConstantSplatVectorFP(GetReg(3), *MRI).has_value());
- EXPECT_TRUE(isConstantOrConstantSplatVectorFP(*MIList[4], *MRI).has_value());
- val = isConstantOrConstantSplatVectorFP(*MIList[4], *MRI).value();
+ EXPECT_TRUE(isConstantOrConstantSplatVectorFP(GetReg(4), *MRI).has_value());
+ val = isConstantOrConstantSplatVectorFP(GetReg(4), *MRI).value();
EXPECT_EQ(2.0, val.convertToFloat());
- EXPECT_FALSE(isConstantOrConstantSplatVectorFP(*MIList[5], *MRI).has_value());
+ EXPECT_FALSE(isConstantOrConstantSplatVectorFP(GetReg(5), *MRI).has_value());
- EXPECT_TRUE(isConstantOrConstantSplatVectorFP(*MIList[6], *MRI).has_value());
- val = isConstantOrConstantSplatVectorFP(*MIList[6], *MRI).value();
+ EXPECT_TRUE(isConstantOrConstantSplatVectorFP(GetReg(6), *MRI).has_value());
+ val = isConstantOrConstantSplatVectorFP(GetReg(6), *MRI).value();
EXPECT_EQ(0.03, val.convertToDouble());
- EXPECT_FALSE(isConstantOrConstantSplatVectorFP(*MIList[7], *MRI).has_value());
+ EXPECT_FALSE(isConstantOrConstantSplatVectorFP(GetReg(7), *MRI).has_value());
- EXPECT_TRUE(isConstantOrConstantSplatVectorFP(*MIList[8], *MRI).has_value());
- val = isConstantOrConstantSplatVectorFP(*MIList[8], *MRI).value();
+ EXPECT_TRUE(isConstantOrConstantSplatVectorFP(GetReg(8), *MRI).has_value());
+ val = isConstantOrConstantSplatVectorFP(GetReg(8), *MRI).value();
EXPECT_EQ(2.0, val.convertToFloat());
- EXPECT_TRUE(isConstantOrConstantSplatVectorFP(*MIList[9], *MRI).has_value());
- val = isConstantOrConstantSplatVectorFP(*MIList[9], *MRI).value();
+ EXPECT_TRUE(isConstantOrConstantSplatVectorFP(GetReg(9), *MRI).has_value());
+ val = isConstantOrConstantSplatVectorFP(GetReg(9), *MRI).value();
EXPECT_EQ(0.03, val.convertToDouble());
- EXPECT_FALSE(
- isConstantOrConstantSplatVectorFP(*MIList[10], *MRI).has_value());
+ EXPECT_FALSE(isConstantOrConstantSplatVectorFP(GetReg(10), *MRI).has_value());
- EXPECT_FALSE(
- isConstantOrConstantSplatVectorFP(*MIList[11], *MRI).has_value());
+ EXPECT_FALSE(isConstantOrConstantSplatVectorFP(GetReg(11), *MRI).has_value());
- EXPECT_FALSE(
- isConstantOrConstantSplatVectorFP(*MIList[12], *MRI).has_value());
+ EXPECT_FALSE(isConstantOrConstantSplatVectorFP(GetReg(12), *MRI).has_value());
- EXPECT_FALSE(
- isConstantOrConstantSplatVectorFP(*MIList[13], *MRI).has_value());
+ EXPECT_FALSE(isConstantOrConstantSplatVectorFP(GetReg(13), *MRI).has_value());
- EXPECT_FALSE(
- isConstantOrConstantSplatVectorFP(*MIList[14], *MRI).has_value());
+ EXPECT_FALSE(isConstantOrConstantSplatVectorFP(GetReg(14), *MRI).has_value());
- EXPECT_FALSE(
- isConstantOrConstantSplatVectorFP(*MIList[15], *MRI).has_value());
+ EXPECT_FALSE(isConstantOrConstantSplatVectorFP(GetReg(15), *MRI).has_value());
}
}
>From 7fd17bc6a151b56af8987cf4b4796cd4463312fd Mon Sep 17 00:00:00 2001
From: Mateusz Chudyk <mateusz.chudyk at intel.com>
Date: Tue, 14 Jul 2026 11:23:59 +0200
Subject: [PATCH 4/4] Change API of isConstantOrConstantSplatVector
---
llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 5 ++---
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 16 ++++++----------
.../CodeGen/GlobalISel/GISelValueTracking.cpp | 8 ++++----
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 2 +-
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 5 ++---
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 4 ++--
.../GISel/AArch64PostLegalizerCombiner.cpp | 13 +++++--------
7 files changed, 22 insertions(+), 31 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index 48e865960cc65..97d40ac1fdac3 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -545,12 +545,11 @@ getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI);
LLVM_ABI bool isConstantOrConstantVector(MachineInstr &MI,
const MachineRegisterInfo &MRI);
-/// Determines if \p MI defines a constant integer or a splat vector of
+/// Determines if \p Def defines a constant integer or a splat vector of
/// constant integers.
/// \returns the scalar constant or std::nullopt.
LLVM_ABI std::optional<APInt>
-isConstantOrConstantSplatVector(MachineInstr &MI,
- const MachineRegisterInfo &MRI);
+isConstantOrConstantSplatVector(Register Def, const MachineRegisterInfo &MRI);
/// Determines if \p Def defines a float constant integer or a splat vector of
/// float constant integers.
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index dc5de81c682a0..021df6a403bdd 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2290,8 +2290,7 @@ bool CombinerHelper::matchCombineShlOfExtend(MachineInstr &MI,
return false;
Register RHS = MI.getOperand(2).getReg();
- MachineInstr *MIShiftAmt = MRI.getVRegDef(RHS);
- auto MaybeShiftAmtVal = isConstantOrConstantSplatVector(*MIShiftAmt, MRI);
+ auto MaybeShiftAmtVal = isConstantOrConstantSplatVector(RHS, MRI);
if (!MaybeShiftAmtVal)
return false;
@@ -2938,8 +2937,7 @@ bool CombinerHelper::matchInsertExtractVecEltOutOfBounds(
bool CombinerHelper::matchConstantSelectCmp(MachineInstr &MI,
unsigned &OpIdx) const {
GSelect &SelMI = cast<GSelect>(MI);
- auto Cst =
- isConstantOrConstantSplatVector(*MRI.getVRegDef(SelMI.getCondReg()), MRI);
+ auto Cst = isConstantOrConstantSplatVector(SelMI.getCondReg(), MRI);
if (!Cst)
return false;
OpIdx = Cst->isZero() ? 3 : 2;
@@ -3049,8 +3047,7 @@ bool CombinerHelper::matchConstantOp(const MachineOperand &MOP,
int64_t C) const {
if (!MOP.isReg())
return false;
- auto *MI = MRI.getVRegDef(MOP.getReg());
- auto MaybeCst = isConstantOrConstantSplatVector(*MI, MRI);
+ auto MaybeCst = isConstantOrConstantSplatVector(MOP.getReg(), MRI);
return MaybeCst && MaybeCst->getBitWidth() <= 64 &&
MaybeCst->getSExtValue() == C;
}
@@ -5344,7 +5341,6 @@ bool CombinerHelper::tryReassocBinOp(unsigned Opc, Register DstReg,
if (OpLHSDef->getOpcode() != Opc)
return false;
- MachineInstr *OpRHSDef = MRI.getVRegDef(OpRHS);
Register OpLHSLHS = OpLHSDef->getOperand(1).getReg();
Register OpLHSRHS = OpLHSDef->getOperand(2).getReg();
@@ -5352,9 +5348,9 @@ bool CombinerHelper::tryReassocBinOp(unsigned Opc, Register DstReg,
// other constants in the expression tree. Folding is not guaranteed so we
// might have (C1 op C2). In that case do not pull a constant out because it
// won't help and can lead to infinite loops.
- if (isConstantOrConstantSplatVector(*MRI.getVRegDef(OpLHSRHS), MRI) &&
- !isConstantOrConstantSplatVector(*MRI.getVRegDef(OpLHSLHS), MRI)) {
- if (isConstantOrConstantSplatVector(*OpRHSDef, MRI)) {
+ if (isConstantOrConstantSplatVector(OpLHSRHS, MRI) &&
+ !isConstantOrConstantSplatVector(OpLHSLHS, MRI)) {
+ if (isConstantOrConstantSplatVector(OpRHS, MRI)) {
// (Opc (Opc X, C1), C2) -> (Opc X, (Opc C1, C2))
MatchInfo = [=](MachineIRBuilder &B) {
auto NewCst = B.buildInstr(Opc, {OpRHSTy}, {OpLHSRHS, OpRHS});
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 0b2d620899630..95525261bc0b1 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -591,8 +591,8 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
case TargetOpcode::G_ROTL:
case TargetOpcode::G_ROTR: {
- MachineInstr *AmtOpMI = MRI.getVRegDef(MI.getOperand(2).getReg());
- auto MaybeAmtOp = isConstantOrConstantSplatVector(*AmtOpMI, MRI);
+ auto MaybeAmtOp =
+ isConstantOrConstantSplatVector(MI.getOperand(2).getReg(), MRI);
if (!MaybeAmtOp)
break;
@@ -611,8 +611,8 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
}
case TargetOpcode::G_FSHL:
case TargetOpcode::G_FSHR: {
- MachineInstr *AmtOpMI = MRI.getVRegDef(MI.getOperand(3).getReg());
- auto MaybeAmtOp = isConstantOrConstantSplatVector(*AmtOpMI, MRI);
+ auto MaybeAmtOp =
+ isConstantOrConstantSplatVector(MI.getOperand(3).getReg(), MRI);
if (!MaybeAmtOp)
break;
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 021f7233ce3b7..c9e9c7a910c46 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9519,7 +9519,7 @@ LegalizerHelper::lowerVECTOR_COMPRESS(llvm::MachineInstr &MI) {
Register LastWriteVal;
std::optional<APInt> PassthruSplatVal =
- isConstantOrConstantSplatVector(*MRI.getVRegDef(Passthru), MRI);
+ isConstantOrConstantSplatVector(Passthru, MRI);
if (PassthruSplatVal.has_value()) {
LastWriteVal =
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 4ccb7d0e5dd7f..85aec46f3690b 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -1527,12 +1527,11 @@ bool llvm::isConstantOrConstantVector(const MachineInstr &MI,
}
std::optional<APInt>
-llvm::isConstantOrConstantSplatVector(MachineInstr &MI,
+llvm::isConstantOrConstantSplatVector(Register Def,
const MachineRegisterInfo &MRI) {
- Register Def = MI.getOperand(0).getReg();
if (auto C = getIConstantVRegValWithLookThrough(Def, MRI))
return C->Value;
- auto MaybeCst = getIConstantSplatSExtVal(MI, MRI);
+ auto MaybeCst = getIConstantSplatSExtVal(Def, MRI);
if (!MaybeCst)
return std::nullopt;
const unsigned ScalarSize = MRI.getType(Def).getScalarSizeInBits();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index e4e58327ead53..efbb66b561bbf 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -2035,8 +2035,8 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
}
case Intrinsic::aarch64_neon_sqshlu: {
// Check if last operand is constant vector dup
- auto ShiftAmount = isConstantOrConstantSplatVector(
- *MRI.getVRegDef(MI.getOperand(3).getReg()), MRI);
+ auto ShiftAmount =
+ isConstantOrConstantSplatVector(MI.getOperand(3).getReg(), MRI);
if (ShiftAmount) {
// If so, create a new intrinsic with the correct shift amount
MIB.buildInstr(AArch64::G_SQSHLU_I, {MI.getOperand(0)},
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index f9c2256728dc9..c8f461c746cbf 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -320,8 +320,7 @@ bool matchSplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI) {
return false; // Don't split truncating stores.
if (!MRI.hasOneNonDBGUse(Store.getValueReg()))
return false;
- auto MaybeCst = isConstantOrConstantSplatVector(
- *MRI.getVRegDef(Store.getValueReg()), MRI);
+ auto MaybeCst = isConstantOrConstantSplatVector(Store.getValueReg(), MRI);
return MaybeCst && MaybeCst->isZero();
}
@@ -404,12 +403,10 @@ bool matchCombineMulCMLT(MachineInstr &MI, MachineRegisterInfo &MRI,
return false;
// Check the constant splat values
- auto V1 = isConstantOrConstantSplatVector(
- *MRI.getVRegDef(MI.getOperand(2).getReg()), MRI);
- auto V2 = isConstantOrConstantSplatVector(
- *MRI.getVRegDef(AndMI->getOperand(2).getReg()), MRI);
- auto V3 = isConstantOrConstantSplatVector(
- *MRI.getVRegDef(LShrMI->getOperand(2).getReg()), MRI);
+ auto V1 = isConstantOrConstantSplatVector(MI.getOperand(2).getReg(), MRI);
+ auto V2 = isConstantOrConstantSplatVector(AndMI->getOperand(2).getReg(), MRI);
+ auto V3 =
+ isConstantOrConstantSplatVector(LShrMI->getOperand(2).getReg(), MRI);
if (!V1.has_value() || !V2.has_value() || !V3.has_value())
return false;
unsigned HalfSize = DstTy.getScalarSizeInBits() / 2;
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