[llvm] [AMDGPU] Model structured control-flow lane masks as i1 (PR #209158)

[Jay Foad via llvm-commits]

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@@ -3903,24 +3903,24 @@ def int_amdgcn_cooperative_atomic_store_8x16B : AMDGPUCooperativeAtomicStore<llv
 // convergence control tokens. The corresponding MIR pseudos are marked as
 // having side effects, which is sufficient to prevent optimizations without
 // having to mark them as convergent.
-def int_amdgcn_if : Intrinsic<[llvm_i1_ty, llvm_anyint_ty],
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jayfoad wrote:

Why can't that be modelled as a divergent (per-lane) boolean?

https://github.com/llvm/llvm-project/pull/209158