[llvm] [LV] Vectorize bounded (i % 2^N) loads in read only loops w/o RT checks. (PR #207279)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 14 02:08:06 PDT 2026
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/207279
>From 2be1b987388f31e9143ee2430e25f41108fc5706 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Sat, 23 May 2026 14:01:58 +0100
Subject: [PATCH] [LV] Vectorize bounded (i % 2^N) loads in read only loops w/o
RT checks.
Add dedicated handling for loops accessing pointers based on bounded IVs
(like A[i % 2^N]). Currently we already vectorize such loops, but with a
wrap predicate that ensures that i % 2^N does not wrap.
This limits the VF to < 2 ^ N, and in many cases results in dead vector
loops, unless the trip counts are very small.
This patch adds dedicated detection for such loads and a new widening
kind (CM_Widen_Bounded). Loops with such loads can be vectorized without
runtime checks, if the VF >= Bound and Bound % VF == 0. This ensures
that the addresses for a single vector access never wrap.
Note that we need to currently handle this both in legacy widening
decision code and new VPlan-based widening. Without the code in the
legacy decision logic, we would create and add the no-wrap predicate and
with that there's no benefit.
The initial version is limited to read-only loops, which means we do not
need to worry about dependencies yet. I will share follow-ups soon to
support writes as well. To avoid churn, the helper is added to
LoopAccessAnalysis.
---
.../llvm/Analysis/LoopAccessAnalysis.h | 8 +
.../Vectorize/LoopVectorizationLegality.h | 4 +
llvm/lib/Analysis/LoopAccessAnalysis.cpp | 32 +
.../Vectorize/LoopVectorizationLegality.cpp | 17 +-
.../Transforms/Vectorize/LoopVectorize.cpp | 46 +-
.../Transforms/Vectorize/VPlanTransforms.cpp | 41 ++
.../LoopVectorize/AArch64/bounded-load.ll | 681 +++++++++++-------
.../LoopVectorize/bounded-load-predicated.ll | 136 ++--
.../LoopVectorize/bounded-load-user-ic.ll | 182 +++--
.../LoopVectorize/bounded-load-vf-ranges.ll | 338 +++++----
.../Transforms/LoopVectorize/bounded-load.ll | 84 ++-
.../runtime-check-small-bounded-ranges.ll | 10 +-
12 files changed, 982 insertions(+), 597 deletions(-)
diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
index 392321448c895..05a9d606e96a2 100644
--- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
+++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
@@ -919,6 +919,14 @@ getPtrStride(PredicatedScalarEvolution &PSE, Type *AccessTy, Value *Ptr,
const DenseMap<Value *, const SCEV *> &StridesMap, bool Assume,
bool ShouldCheckWrap = true);
+/// If \p PtrSCEV is a bounded access of the form `Base + ElemSize * (i % 2^N)`
+/// where Base is loop invariant in \p L and ElemSize equals the allocation size
+/// of \p AccessTy, returns the bound 2^N.
+LLVM_ABI std::optional<uint64_t> getBoundedAccessBound(const SCEV *PtrSCEV,
+ Type *AccessTy,
+ const Loop *L,
+ ScalarEvolution &SE);
+
/// Returns the distance between the pointers \p PtrA and \p PtrB iff they are
/// compatible and it is possible to calculate the distance between them. This
/// is a simple API that does not depend on the analysis pass.
diff --git a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
index 3e8db73fd79d2..4ea0c037e4489 100644
--- a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+++ b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
@@ -389,6 +389,10 @@ class LoopVectorizationLegality {
/// loop. Do not use after invoking 'createVectorizedLoopSkeleton' (PR34965).
LLVM_ABI int isConsecutivePtr(Type *AccessTy, Value *Ptr) const;
+ /// If \p I is a bounded (i % 2^N) load in a read-only loop, returns its
+ /// bound (2^N).
+ LLVM_ABI std::optional<uint64_t> getBoundedLoadBound(Instruction *I) const;
+
/// Returns true if \p V is invariant across all loop iterations according to
/// SCEV.
LLVM_ABI bool isInvariant(Value *V) const;
diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
index 8d3c66c8fe321..6dc83574a21d3 100644
--- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
@@ -1706,6 +1706,38 @@ llvm::getPtrStride(PredicatedScalarEvolution &PSE, Type *AccessTy, Value *Ptr,
return Stride;
}
+std::optional<uint64_t> llvm::getBoundedAccessBound(const SCEV *PtrSCEV,
+ Type *AccessTy,
+ const Loop *L,
+ ScalarEvolution &SE) {
+ if (AccessTy->isScalableTy())
+ return std::nullopt;
+
+ // `A[i % 2^N]` is `Base + ElemSize * zext({0,+,1}<iN>)`. For a byte
+ // element (ElemSize == 1) the multiply folds away.
+ const SCEV *Base, *Start;
+ const APInt *Scale = nullptr;
+ auto Index = m_scev_ZExt(
+ m_scev_AffineAddRec(m_SCEV(Start), m_scev_One(), m_SpecificLoop(L)));
+ if (!match(PtrSCEV, m_scev_Add(m_scev_Mul(m_scev_APInt(Scale), Index),
+ m_SCEV(Base))) &&
+ !match(PtrSCEV, m_scev_Add(Index, m_SCEV(Base))))
+ return std::nullopt;
+
+ uint64_t AllocSize = L->getHeader()
+ ->getDataLayout()
+ .getTypeAllocSize(AccessTy)
+ .getFixedValue();
+ if (!Start->isZero() || !SE.isLoopInvariant(Base, L) ||
+ (Scale ? *Scale != AllocSize : AllocSize != 1))
+ return std::nullopt;
+
+ unsigned NarrowWidth = SE.getTypeSizeInBits(Start->getType());
+ if (NarrowWidth == 0 || NarrowWidth >= 64)
+ return std::nullopt;
+ return uint64_t(1) << NarrowWidth;
+}
+
std::optional<int64_t> llvm::getPointersDiff(Type *ElemTyA, Value *PtrA,
Type *ElemTyB, Value *PtrB,
const DataLayout &DL,
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
index 8d875b2b6e492..2fe01360c7104 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
@@ -437,9 +437,14 @@ void LoopVectorizationLegality::collectUnitStridePredicates() const {
return;
for (BasicBlock *BB : TheLoop->blocks())
- for (Instruction &I : *BB)
+ for (Instruction &I : *BB) {
+ // Bounded loads use the fast path; skip to avoid the wrap predicate
+ // getPtrStride would register.
+ if (getBoundedLoadBound(&I))
+ continue;
if (Value *Ptr = getLoadStorePointerOperand(&I))
isConsecutivePtr(getLoadStoreType(&I), Ptr);
+ }
}
int LoopVectorizationLegality::isConsecutivePtr(Type *AccessTy,
@@ -461,6 +466,16 @@ int LoopVectorizationLegality::isConsecutivePtr(Type *AccessTy,
return 0;
}
+std::optional<uint64_t>
+LoopVectorizationLegality::getBoundedLoadBound(Instruction *I) const {
+ auto *LI = dyn_cast<LoadInst>(I);
+ if (!LI || LAI->getNumStores() != 0)
+ return std::nullopt;
+ Value *Ptr = LI->getPointerOperand();
+ return llvm::getBoundedAccessBound(PSE.getSCEV(Ptr), LI->getType(), TheLoop,
+ *PSE.getSE());
+}
+
bool LoopVectorizationLegality::isInvariant(Value *V) const {
return LAI->isInvariant(V);
}
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 1929f52ae7d95..11c08087da657 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -882,6 +882,7 @@ class LoopVectorizationCostModel {
enum InstWidening {
CM_Unknown,
CM_Widen, // For consecutive accesses with stride +1.
+ CM_Widen_Bounded, // For bounded (i % 2^N) loads in read-only loops.
CM_Widen_Reverse, // For consecutive accesses with stride -1.
CM_Interleave,
CM_GatherScatter,
@@ -1055,8 +1056,8 @@ class LoopVectorizationCostModel {
getDivRemSpeculationCost(Instruction *I, ElementCount VF);
/// If \p I is a memory instruction with a consecutive pointer that can be
- /// widened, returns the widening kind (CM_Widen or CM_Widen_Reverse) and
- /// std::nullopt otherwise.
+ /// widened, returns the widening kind (CM_Widen, CM_Widen_Reverse,
+ /// CM_Widen_Bounded) and std::nullopt otherwise.
std::optional<InstWidening> memoryInstructionCanBeWidened(Instruction *I,
ElementCount VF);
@@ -2421,8 +2422,10 @@ bool LoopVectorizationCostModel::isScalarWithPredication(Instruction *I,
}
case Instruction::Load:
case Instruction::Store: {
- bool IsConsecutive = Legal->isConsecutivePtr(getLoadStoreType(I),
- getLoadStorePointerOperand(I));
+ bool IsConsecutive =
+ Legal->getBoundedLoadBound(I).has_value() ||
+ Legal->isConsecutivePtr(getLoadStoreType(I),
+ getLoadStorePointerOperand(I)) != 0;
return !(IsConsecutive && Config.isLegalMaskedLoadOrStore(I, VF)) &&
!Config.isLegalGatherOrScatter(I, VF);
}
@@ -2662,20 +2665,27 @@ LoopVectorizationCostModel::memoryInstructionCanBeWidened(Instruction *I,
auto *Ptr = getLoadStorePointerOperand(I);
auto *ScalarTy = getLoadStoreType(I);
- // In order to be widened, the pointer should be consecutive, first of all.
- int Stride = Legal->isConsecutivePtr(ScalarTy, Ptr);
- if (!Stride)
+ // If the instruction's allocated size doesn't equal it's type size, it
+ // requires padding and will be scalarized.
+ auto &DL = I->getDataLayout();
+ if (hasIrregularType(ScalarTy, DL))
return std::nullopt;
- // If the instruction is a store located in a predicated block, it will be
- // scalarized.
+ // If the instruction is located in a predicated block, it will be scalarized.
if (isScalarWithPredication(I, VF))
return std::nullopt;
- // If the instruction's allocated size doesn't equal it's type size, it
- // requires padding and will be scalarized.
- auto &DL = I->getDataLayout();
- if (hasIrregularType(ScalarTy, DL))
+ // Widen a bounded (i % 2^N) load in a read-only loop as a consecutive
+ // vector load when VF divides the bound.
+ if (std::optional<uint64_t> Bound = Legal->getBoundedLoadBound(I);
+ Bound && VF.isFixed()) {
+ if (VF.getFixedValue() <= *Bound && *Bound % VF.getFixedValue() == 0)
+ return CM_Widen_Bounded;
+ return std::nullopt;
+ }
+
+ int Stride = Legal->isConsecutivePtr(ScalarTy, Ptr);
+ if (!Stride)
return std::nullopt;
return Stride == 1 ? CM_Widen : CM_Widen_Reverse;
@@ -2772,6 +2782,7 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) {
return true;
return (WideningDecision == CM_Widen ||
+ WideningDecision == CM_Widen_Bounded ||
WideningDecision == CM_Widen_Reverse ||
WideningDecision == CM_Interleave);
};
@@ -4287,7 +4298,8 @@ LoopVectorizationCostModel::getMemInstScalarizationCost(Instruction *I,
InstructionCost LoopVectorizationCostModel::getConsecutiveMemOpCost(
Instruction *I, ElementCount VF, InstWidening Kind) {
- assert((Kind == CM_Widen || Kind == CM_Widen_Reverse) &&
+ assert((Kind == CM_Widen || Kind == CM_Widen_Reverse ||
+ Kind == CM_Widen_Bounded) &&
"Expected a consecutive widening decision");
Type *ValTy = getLoadStoreType(I);
auto *VectorTy = cast<VectorType>(toVectorTy(ValTy, VF));
@@ -4859,7 +4871,8 @@ void LoopVectorizationCostModel::setCostBasedWideningDecision(ElementCount VF) {
// instead changed here when we know this is the case.
InstWidening Decision = getWideningDecision(I, VF);
if (!isPredicatedInst(I) &&
- (Decision == CM_Widen || Decision == CM_Widen_Reverse ||
+ (Decision == CM_Widen || Decision == CM_Widen_Bounded ||
+ Decision == CM_Widen_Reverse ||
(!isUniformMemOp(*I, VF) && Decision == CM_Scalarize))) {
// Scalarize a widened load of address or update the cost of a scalar
// load of an address.
@@ -5270,6 +5283,7 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I,
return TTI::CastContextHint::Interleave;
case LoopVectorizationCostModel::CM_Scalarize:
case LoopVectorizationCostModel::CM_Widen:
+ case LoopVectorizationCostModel::CM_Widen_Bounded:
return isPredicatedInst(I) ? TTI::CastContextHint::Masked
: TTI::CastContextHint::Normal;
case LoopVectorizationCostModel::CM_Widen_Reverse:
@@ -6187,6 +6201,8 @@ VPRecipeBase *VPRecipeBuilder::tryToWidenMemory(VPInstruction *VPI,
// reverse consecutive.
LoopVectorizationCostModel::InstWidening Decision =
CM.getWideningDecision(I, Range.Start);
+ assert(Decision != LoopVectorizationCostModel::CM_Widen_Bounded &&
+ "bounded loads must be widened in makeMemOpWideningDecisions");
bool Reverse = Decision == LoopVectorizationCostModel::CM_Widen_Reverse;
bool Consecutive =
Reverse || Decision == LoopVectorizationCostModel::CM_Widen;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 4da74c5146c52..6f41b95a5d1d8 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -7332,6 +7332,35 @@ static std::optional<int64_t> getConstantStride(VPValue *Addr, Type *AccessTy,
return getStrideFromAddRec(AddRec, L, AccessTy, /*Ptr=*/nullptr, PSE);
}
+/// Check if \p VPI is a bounded (i % 2^N) load we can widen. This requires the
+/// vector factor to divide the bound, so that each VF-wide load stays within a
+/// single 2^N window.
+static bool canCreateBoundedLoad(VPInstruction *VPI, VFRange &Range,
+ VPCostContext &Ctx) {
+ if (VPI->getOpcode() != Instruction::Load)
+ return false;
+
+ Type *ScalarTy = VPI->getScalarType();
+ if (hasIrregularType(ScalarTy, Ctx.L->getHeader()->getDataLayout()))
+ return false;
+
+ const SCEV *PtrSCEV =
+ vputils::getSCEVExprForVPValue(VPI->getOperand(0), Ctx.PSE, Ctx.L);
+ std::optional<uint64_t> Bound =
+ getBoundedAccessBound(PtrSCEV, ScalarTy, Ctx.L, *Ctx.PSE.getSE());
+ if (!Bound)
+ return false;
+
+ // Only widen for VFs that divide the bound, so each VF-wide load stays within
+ // a single window and does not wrap.
+ auto DividesBound = [&](ElementCount VF) {
+ return VF.isFixed() && VF.getFixedValue() <= *Bound &&
+ *Bound % VF.getFixedValue() == 0;
+ };
+ return LoopVectorizationPlanner::getDecisionAndClampRange(DividesBound,
+ Range);
+}
+
void VPlanTransforms::makeMemOpWideningDecisions(VPlan &Plan, VFRange &Range,
VPRecipeBuilder &RecipeBuilder,
VPCostContext &CostCtx) {
@@ -7353,6 +7382,9 @@ void VPlanTransforms::makeMemOpWideningDecisions(VPlan &Plan, VFRange &Range,
// Few helpers to process different kinds of memory operations.
+ bool LoopHasStore = any_of(
+ MemOps, [](VPInstruction *VPI) { return VPI->mayWriteToMemory(); });
+
// To be used as argument to `VPlanTransforms::runPass` which explicitly
// specified pass name, hence `VPlan &` parameter.
auto ProcessSubset = [&](VPlan &, auto ProcessVPInst) {
@@ -7452,6 +7484,15 @@ void VPlanTransforms::makeMemOpWideningDecisions(VPlan &Plan, VFRange &Range,
return false;
bool IsLoad = VPI->getOpcode() == Instruction::Load;
+ if (IsLoad && !LoopHasStore &&
+ canCreateBoundedLoad(VPI, Range, CostCtx)) {
+ auto *Load = cast<LoadInst>(VPI->getUnderlyingInstr());
+ auto *LoadR = new VPWidenLoadRecipe(
+ *Load, VPI->getOperand(0), /*Mask=*/nullptr,
+ /*Consecutive=*/true, *VPI, Load->getDebugLoc());
+ return ReplaceWith(VPI, LoadR);
+ }
+
VPValue *Ptr = VPI->getOperand(!IsLoad);
Type *ScalarTy =
IsLoad ? VPI->getScalarType() : VPI->getOperand(0)->getScalarType();
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll b/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
index fd1456aab8b49..e540f1ee4f0b0 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
@@ -7,97 +7,63 @@ define i32 @bounded_load_reduction_bound2(ptr %A, i32 %N) {
; CHECK-LABEL: define i32 @bounded_load_reduction_bound2(
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[TMP3]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i32 [[TMP0]], 1
-; CHECK-NEXT: [[TMP10:%.*]] = or i1 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: br i1 [[TMP10]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH1:.*]]
-; CHECK: [[VECTOR_PH1]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 8
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = urem i32 [[INDEX]], 2
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 -3
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 -7
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 -11
-; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 -15
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4
-; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP12]], align 4
-; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP8]], align 4
-; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4
-; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[REVERSE3:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD2]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[REVERSE9:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD6]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[REVERSE10:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD7]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI]], [[REVERSE]]
-; CHECK-NEXT: [[TMP9]] = add <4 x i32> [[VEC_PHI1]], [[REVERSE3]]
-; CHECK-NEXT: [[TMP14]] = add <4 x i32> [[VEC_PHI3]], [[REVERSE9]]
-; CHECK-NEXT: [[TMP13]] = add <4 x i32> [[VEC_PHI4]], [[REVERSE10]]
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[INDEX]], 2
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[INDEX]], 6
+; CHECK-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = urem i32 [[TMP7]], 2
+; CHECK-NEXT: [[TMP5:%.*]] = urem i32 [[TMP11]], 2
+; CHECK-NEXT: [[TMP6:%.*]] = urem i32 [[TMP15]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP4]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP6]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4
+; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <2 x i32>, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i32>, ptr [[TMP9]], align 4
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i32>, ptr [[TMP10]], align 4
+; CHECK-NEXT: [[TMP2]] = add <2 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP12]] = add <2 x i32> [[VEC_PHI1]], [[WIDE_LOAD4]]
+; CHECK-NEXT: [[TMP13]] = add <2 x i32> [[VEC_PHI2]], [[WIDE_LOAD5]]
+; CHECK-NEXT: [[TMP14]] = add <2 x i32> [[VEC_PHI3]], [[WIDE_LOAD6]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP9]], [[TMP11]]
-; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP14]], [[BIN_RDX]]
-; CHECK-NEXT: [[BIN_RDX12:%.*]] = add <4 x i32> [[TMP13]], [[BIN_RDX11]]
-; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX12]])
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[TMP12]], [[TMP2]]
+; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <2 x i32> [[TMP13]], [[BIN_RDX]]
+; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <2 x i32> [[TMP14]], [[BIN_RDX7]]
+; CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX8]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
-; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
-; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF]], 4
-; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
-; CHECK: [[VEC_EPILOG_PH]]:
-; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP15]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
-; CHECK-NEXT: [[N_MOD_VF13:%.*]] = urem i32 [[N]], 4
-; CHECK-NEXT: [[N_VEC14:%.*]] = sub i32 [[N]], [[N_MOD_VF13]]
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i32> zeroinitializer, i32 [[BC_MERGE_RDX]], i32 0
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP16]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[INDEX15:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT19:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[VEC_PHI16:%.*]] = phi <4 x i32> [ [[TMP16]], %[[VEC_EPILOG_PH]] ], [ [[TMP20:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[TMP23:%.*]] = urem i32 [[INDEX15]], 2
-; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP23]]
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i64 -3
-; CHECK-NEXT: [[WIDE_LOAD17:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4
-; CHECK-NEXT: [[REVERSE18:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD17]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[TMP20]] = add <4 x i32> [[VEC_PHI16]], [[REVERSE18]]
-; CHECK-NEXT: [[INDEX_NEXT19]] = add nuw i32 [[INDEX15]], 4
-; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[INDEX_NEXT19]], [[N_VEC14]]
-; CHECK-NEXT: br i1 [[TMP21]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
-; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[TMP22:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP20]])
-; CHECK-NEXT: [[CMP_N20:%.*]] = icmp eq i32 [[N]], [[N_VEC14]]
-; CHECK-NEXT: br i1 [[CMP_N20]], label %[[EXIT]], label %[[SCALAR_PH]]
-; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC14]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX21:%.*]] = phi i32 [ [[TMP22]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP15]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: br label %[[LOOP1:.*]]
-; CHECK: [[LOOP1]]:
-; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP1]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX21]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP1]] ]
-; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV1]], 2
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 2
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[GEP]], align 4
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV1]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP1]] ], [ [[TMP15]], %[[MIDDLE_BLOCK]] ], [ [[TMP22]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP16]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i32 [[R]]
;
entry:
@@ -123,88 +89,90 @@ define i32 @bounded_load_reduction_bound4(ptr %A, i32 %N) {
; CHECK-LABEL: define i32 @bounded_load_reduction_bound4(
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[TMP7]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH1:.*]]
; CHECK: [[VECTOR_PH1]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
+; CHECK-NEXT: [[N_MOD_VF1:%.*]] = urem i32 [[N]], 16
+; CHECK-NEXT: [[N_VEC1:%.*]] = sub i32 [[N]], [[N_MOD_VF1]]
+; CHECK-NEXT: br label %[[VECTOR_BODY1:.*]]
+; CHECK: [[VECTOR_BODY1]]:
+; CHECK-NEXT: [[INDEX1:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[INDEX1]], 4
+; CHECK-NEXT: [[TMP19:%.*]] = add i32 [[INDEX1]], 8
+; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[INDEX1]], 12
+; CHECK-NEXT: [[TMP21:%.*]] = urem i32 [[INDEX1]], 4
+; CHECK-NEXT: [[TMP22:%.*]] = urem i32 [[TMP18]], 4
+; CHECK-NEXT: [[TMP5:%.*]] = urem i32 [[TMP19]], 4
+; CHECK-NEXT: [[TMP6:%.*]] = urem i32 [[TMP20]], 4
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP21]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP22]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP6]]
+; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP9]], align 4
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4
+; CHECK-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI1]], [[WIDE_LOAD1]]
+; CHECK-NEXT: [[TMP12]] = add <4 x i32> [[VEC_PHI2]], [[WIDE_LOAD5]]
+; CHECK-NEXT: [[TMP13]] = add <4 x i32> [[VEC_PHI3]], [[WIDE_LOAD6]]
+; CHECK-NEXT: [[TMP14]] = add <4 x i32> [[VEC_PHI4]], [[WIDE_LOAD7]]
+; CHECK-NEXT: [[INDEX_NEXT1]] = add nuw i32 [[INDEX1]], 16
+; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[INDEX_NEXT1]], [[N_VEC1]]
+; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK1:.*]], label %[[VECTOR_BODY1]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK1]]:
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP12]], [[TMP11]]
+; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP13]], [[BIN_RDX]]
+; CHECK-NEXT: [[BIN_RDX9:%.*]] = add <4 x i32> [[TMP14]], [[BIN_RDX8]]
+; CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX9]])
+; CHECK-NEXT: [[CMP_N1:%.*]] = icmp eq i32 [[N]], [[N_VEC1]]
+; CHECK-NEXT: br i1 [[CMP_N1]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
+; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
+; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF1]], 4
+; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF5:![0-9]+]]
+; CHECK: [[VEC_EPILOG_PH]]:
+; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC1]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP16]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x i32> zeroinitializer, i32 [[BC_MERGE_RDX]], i32 0
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[INDEX]], 4
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 4
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 8
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 12
-; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4
-; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4
-; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP14]], align 4
-; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4
-; CHECK-NEXT: [[TMP9]] = add <4 x i32> [[VEC_PHI1]], [[WIDE_LOAD2]]
-; CHECK-NEXT: [[TMP8]] = add <4 x i32> [[VEC_PHI2]], [[WIDE_LOAD3]]
-; CHECK-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI3]], [[WIDE_LOAD6]]
-; CHECK-NEXT: [[TMP10]] = add <4 x i32> [[VEC_PHI4]], [[WIDE_LOAD7]]
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ [[TMP17]], %[[VEC_EPILOG_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
+; CHECK-NEXT: [[TMP2]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP8]], [[TMP9]]
-; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP11]], [[BIN_RDX]]
-; CHECK-NEXT: [[BIN_RDX9:%.*]] = add <4 x i32> [[TMP10]], [[BIN_RDX8]]
-; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX9]])
+; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
-; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
-; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF]], 4
-; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3]]
-; CHECK: [[VEC_EPILOG_PH]]:
-; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP12]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
-; CHECK-NEXT: [[N_MOD_VF10:%.*]] = urem i32 [[N]], 4
-; CHECK-NEXT: [[N_VEC11:%.*]] = sub i32 [[N]], [[N_MOD_VF10]]
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> zeroinitializer, i32 [[BC_MERGE_RDX]], i32 0
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ [[N_VEC1]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX17:%.*]] = phi i32 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ [[TMP16]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[INDEX12:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT15:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[VEC_PHI13:%.*]] = phi <4 x i32> [ [[TMP13]], %[[VEC_EPILOG_PH]] ], [ [[TMP16:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[TMP19:%.*]] = urem i32 [[INDEX12]], 4
-; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP19]]
-; CHECK-NEXT: [[WIDE_LOAD14:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4
-; CHECK-NEXT: [[TMP16]] = add <4 x i32> [[VEC_PHI13]], [[WIDE_LOAD14]]
-; CHECK-NEXT: [[INDEX_NEXT15]] = add nuw i32 [[INDEX12]], 4
-; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT15]], [[N_VEC11]]
-; CHECK-NEXT: br i1 [[TMP17]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
-; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP16]])
-; CHECK-NEXT: [[CMP_N16:%.*]] = icmp eq i32 [[N]], [[N_VEC11]]
-; CHECK-NEXT: br i1 [[CMP_N16]], label %[[EXIT]], label %[[SCALAR_PH]]
-; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC11]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX17:%.*]] = phi i32 [ [[TMP18]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP12]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: br label %[[LOOP1:.*]]
-; CHECK: [[LOOP1]]:
-; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP1]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX17]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP1]] ]
-; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV1]], 4
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX17]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[GEP]], align 4
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV1]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP1]] ], [ [[TMP12]], %[[MIDDLE_BLOCK]] ], [ [[TMP18]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP16]], %[[MIDDLE_BLOCK1]] ], [ [[TMP4]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i32 [[R]]
;
entry:
@@ -229,79 +197,91 @@ exit:
define i16 @bounded_load_reduction_bound4_i16(ptr %A, i32 %N) {
; CHECK-LABEL: define i16 @bounded_load_reduction_bound4_i16(
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
-; CHECK-NEXT: [[ITER_CHECK:.*]]:
+; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
-; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
-; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
+; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH1:.*]]
+; CHECK: [[VECTOR_PH1]]:
+; CHECK-NEXT: [[N_MOD_VF1:%.*]] = urem i32 [[N]], 16
+; CHECK-NEXT: [[N_VEC1:%.*]] = sub i32 [[N]], [[N_MOD_VF1]]
+; CHECK-NEXT: br label %[[VECTOR_BODY1:.*]]
+; CHECK: [[VECTOR_BODY1]]:
+; CHECK-NEXT: [[INDEX1:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i16> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i16> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i16> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i16> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[INDEX1]], 4
+; CHECK-NEXT: [[TMP19:%.*]] = add i32 [[INDEX1]], 8
+; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[INDEX1]], 12
+; CHECK-NEXT: [[TMP21:%.*]] = urem i32 [[INDEX1]], 4
+; CHECK-NEXT: [[TMP22:%.*]] = urem i32 [[TMP18]], 4
+; CHECK-NEXT: [[TMP5:%.*]] = urem i32 [[TMP19]], 4
+; CHECK-NEXT: [[TMP6:%.*]] = urem i32 [[TMP20]], 4
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP21]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP22]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP6]]
+; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i16>, ptr [[TMP7]], align 2
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i16>, ptr [[TMP8]], align 2
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i16>, ptr [[TMP9]], align 2
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i16>, ptr [[TMP10]], align 2
+; CHECK-NEXT: [[TMP11]] = add <4 x i16> [[VEC_PHI1]], [[WIDE_LOAD1]]
+; CHECK-NEXT: [[TMP12]] = add <4 x i16> [[VEC_PHI2]], [[WIDE_LOAD5]]
+; CHECK-NEXT: [[TMP13]] = add <4 x i16> [[VEC_PHI3]], [[WIDE_LOAD6]]
+; CHECK-NEXT: [[TMP14]] = add <4 x i16> [[VEC_PHI4]], [[WIDE_LOAD7]]
+; CHECK-NEXT: [[INDEX_NEXT1]] = add nuw i32 [[INDEX1]], 16
+; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[INDEX_NEXT1]], [[N_VEC1]]
+; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK1:.*]], label %[[VECTOR_BODY1]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK1]]:
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i16> [[TMP12]], [[TMP11]]
+; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i16> [[TMP13]], [[BIN_RDX]]
+; CHECK-NEXT: [[BIN_RDX9:%.*]] = add <4 x i16> [[TMP14]], [[BIN_RDX8]]
+; CHECK-NEXT: [[TMP16:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[BIN_RDX9]])
+; CHECK-NEXT: [[CMP_N1:%.*]] = icmp eq i32 [[N]], [[N_VEC1]]
+; CHECK-NEXT: br i1 [[CMP_N1]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
+; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
+; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF1]], 4
+; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF5]]
+; CHECK: [[VEC_EPILOG_PH]]:
+; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC1]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP16]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x i16> zeroinitializer, i16 [[BC_MERGE_RDX]], i32 0
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <8 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <8 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP15:%.*]] = urem i32 [[INDEX]], 4
-; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP15]]
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i16, ptr [[TMP16]], i64 8
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[TMP16]], align 2
-; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i16>, ptr [[TMP4]], align 2
-; CHECK-NEXT: [[TMP5]] = add <8 x i16> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP12]] = add <8 x i16> [[VEC_PHI2]], [[WIDE_LOAD3]]
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i16> [ [[TMP17]], %[[VEC_EPILOG_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP0]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP1]], align 2
+; CHECK-NEXT: [[TMP2]] = add <4 x i16> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <8 x i16> [[TMP12]], [[TMP5]]
-; CHECK-NEXT: [[TMP14:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[BIN_RDX]])
-; CHECK-NEXT: [[CMP_N1:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N1]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
-; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
-; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF]], 4
-; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3]]
-; CHECK: [[VEC_EPILOG_PH]]:
-; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX1:%.*]] = phi i16 [ [[TMP14]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
-; CHECK-NEXT: [[N_MOD_VF4:%.*]] = urem i32 [[N]], 4
-; CHECK-NEXT: [[N_VEC5:%.*]] = sub i32 [[N]], [[N_MOD_VF4]]
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i16> zeroinitializer, i16 [[BC_MERGE_RDX1]], i32 0
-; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]
-; CHECK: [[VEC_EPILOG_VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX6:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT9:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i16> [ [[TMP9]], %[[VEC_EPILOG_PH]] ], [ [[TMP6:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP10:%.*]] = urem i32 [[INDEX6]], 4
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP10]]
-; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i16>, ptr [[TMP11]], align 2
-; CHECK-NEXT: [[TMP6]] = add <4 x i16> [[VEC_PHI1]], [[WIDE_LOAD2]]
-; CHECK-NEXT: [[INDEX_NEXT9]] = add nuw i32 [[INDEX6]], 4
-; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT9]], [[N_VEC5]]
-; CHECK-NEXT: br i1 [[TMP13]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
-; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[TMP8:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[TMP6]])
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC5]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
-; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC5]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX11:%.*]] = phi i16 [ [[TMP8]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP14]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[TMP2]])
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ [[N_VEC1]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX17:%.*]] = phi i16 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ [[TMP16]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i16 [ [[BC_MERGE_RDX11]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i16 [ [[BC_MERGE_RDX17]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[BOUNDED]]
; CHECK-NEXT: [[LV:%.*]] = load i16, ptr [[GEP]], align 2
; CHECK-NEXT: [[SUM_NEXT]] = add i16 [[SUM]], [[LV]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[R:%.*]] = phi i16 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP14]], %[[MIDDLE_BLOCK]] ], [ [[TMP8]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[R:%.*]] = phi i16 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP16]], %[[MIDDLE_BLOCK1]] ], [ [[TMP4]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i16 [[R]]
;
entry:
@@ -323,72 +303,83 @@ exit:
ret i16 %r
}
-define i32 @bounded_user_ic_capped(ptr %A, i32 %N) {
-; CHECK-LABEL: define i32 @bounded_user_ic_capped(
+; Test with forced interleave count 8 via metadata.
+define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
+; CHECK-LABEL: define i32 @bounded_user_ic_exceeds_window(
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 32
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 32
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[INDEX]], 4
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 4
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 8
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 12
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 16
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 20
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 24
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 28
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4
-; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4
-; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
-; CHECK-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4
-; CHECK-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4
-; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <4 x i32>, ptr [[TMP8]], align 4
-; CHECK-NEXT: [[WIDE_LOAD13:%.*]] = load <4 x i32>, ptr [[TMP9]], align 4
-; CHECK-NEXT: [[WIDE_LOAD14:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4
-; CHECK-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP12]] = add <4 x i32> [[VEC_PHI1]], [[WIDE_LOAD8]]
-; CHECK-NEXT: [[TMP13]] = add <4 x i32> [[VEC_PHI2]], [[WIDE_LOAD9]]
-; CHECK-NEXT: [[TMP14]] = add <4 x i32> [[VEC_PHI3]], [[WIDE_LOAD10]]
-; CHECK-NEXT: [[TMP15]] = add <4 x i32> [[VEC_PHI4]], [[WIDE_LOAD11]]
-; CHECK-NEXT: [[TMP16]] = add <4 x i32> [[VEC_PHI5]], [[WIDE_LOAD12]]
-; CHECK-NEXT: [[TMP17]] = add <4 x i32> [[VEC_PHI6]], [[WIDE_LOAD13]]
-; CHECK-NEXT: [[TMP18]] = add <4 x i32> [[VEC_PHI7]], [[WIDE_LOAD14]]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP28:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP30:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 12
+; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 16
+; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 20
+; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[INDEX]], 24
+; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 28
+; CHECK-NEXT: [[TMP7:%.*]] = urem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP8:%.*]] = urem i32 [[TMP0]], 4
+; CHECK-NEXT: [[TMP9:%.*]] = urem i32 [[TMP1]], 4
+; CHECK-NEXT: [[TMP10:%.*]] = urem i32 [[TMP2]], 4
+; CHECK-NEXT: [[TMP11:%.*]] = urem i32 [[TMP3]], 4
+; CHECK-NEXT: [[TMP12:%.*]] = urem i32 [[TMP4]], 4
+; CHECK-NEXT: [[TMP13:%.*]] = urem i32 [[TMP5]], 4
+; CHECK-NEXT: [[TMP14:%.*]] = urem i32 [[TMP6]], 4
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP7]]
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP8]]
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP9]]
+; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP10]]
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP11]]
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP12]]
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP13]]
+; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP14]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4
+; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4
+; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4
+; CHECK-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i32>, ptr [[TMP18]], align 4
+; CHECK-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4
+; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <4 x i32>, ptr [[TMP20]], align 4
+; CHECK-NEXT: [[WIDE_LOAD13:%.*]] = load <4 x i32>, ptr [[TMP21]], align 4
+; CHECK-NEXT: [[WIDE_LOAD14:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4
+; CHECK-NEXT: [[TMP23]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP24]] = add <4 x i32> [[VEC_PHI1]], [[WIDE_LOAD8]]
+; CHECK-NEXT: [[TMP25]] = add <4 x i32> [[VEC_PHI2]], [[WIDE_LOAD9]]
+; CHECK-NEXT: [[TMP26]] = add <4 x i32> [[VEC_PHI3]], [[WIDE_LOAD10]]
+; CHECK-NEXT: [[TMP27]] = add <4 x i32> [[VEC_PHI4]], [[WIDE_LOAD11]]
+; CHECK-NEXT: [[TMP28]] = add <4 x i32> [[VEC_PHI5]], [[WIDE_LOAD12]]
+; CHECK-NEXT: [[TMP29]] = add <4 x i32> [[VEC_PHI6]], [[WIDE_LOAD13]]
+; CHECK-NEXT: [[TMP30]] = add <4 x i32> [[VEC_PHI7]], [[WIDE_LOAD14]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 32
-; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK-NEXT: [[TMP31:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP31]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[BIN_RDX15:%.*]] = add <4 x i32> [[TMP13]], [[BIN_RDX]]
-; CHECK-NEXT: [[BIN_RDX16:%.*]] = add <4 x i32> [[TMP14]], [[BIN_RDX15]]
-; CHECK-NEXT: [[BIN_RDX17:%.*]] = add <4 x i32> [[TMP15]], [[BIN_RDX16]]
-; CHECK-NEXT: [[BIN_RDX18:%.*]] = add <4 x i32> [[TMP16]], [[BIN_RDX17]]
-; CHECK-NEXT: [[BIN_RDX19:%.*]] = add <4 x i32> [[TMP17]], [[BIN_RDX18]]
-; CHECK-NEXT: [[BIN_RDX20:%.*]] = add <4 x i32> [[TMP18]], [[BIN_RDX19]]
-; CHECK-NEXT: [[TMP20:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX20]])
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP24]], [[TMP23]]
+; CHECK-NEXT: [[BIN_RDX15:%.*]] = add <4 x i32> [[TMP25]], [[BIN_RDX]]
+; CHECK-NEXT: [[BIN_RDX16:%.*]] = add <4 x i32> [[TMP26]], [[BIN_RDX15]]
+; CHECK-NEXT: [[BIN_RDX17:%.*]] = add <4 x i32> [[TMP27]], [[BIN_RDX16]]
+; CHECK-NEXT: [[BIN_RDX18:%.*]] = add <4 x i32> [[TMP28]], [[BIN_RDX17]]
+; CHECK-NEXT: [[BIN_RDX19:%.*]] = add <4 x i32> [[TMP29]], [[BIN_RDX18]]
+; CHECK-NEXT: [[BIN_RDX20:%.*]] = add <4 x i32> [[TMP30]], [[BIN_RDX19]]
+; CHECK-NEXT: [[TMP32:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX20]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP20]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP32]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
@@ -399,9 +390,9 @@ define i32 @bounded_user_ic_capped(ptr %A, i32 %N) {
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP20]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP32]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i32 [[SUM_NEXT_LCSSA]]
;
entry:
@@ -442,30 +433,30 @@ define i32 @scalable_vf_rejected(ptr %A, i64 %N) #0 {
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP6:%.*]] = urem i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP6]]
-; CHECK-NEXT: [[TMP10:%.*]] = shl nuw nsw i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = shl nuw nsw i64 [[TMP4]], 1
; CHECK-NEXT: [[TMP9:%.*]] = mul nuw nsw i64 [[TMP4]], 3
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 [[TMP10]]
-; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 [[TMP9]]
-; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
-; CHECK-NEXT: [[WIDE_MASKED_GATHER2:%.*]] = load <vscale x 4 x i32>, ptr [[TMP8]], align 4
-; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x i32>, ptr [[TMP14]], align 4
-; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <vscale x 4 x i32>, ptr [[TMP17]], align 4
-; CHECK-NEXT: [[TMP11]] = add <vscale x 4 x i32> [[VEC_PHI]], [[WIDE_MASKED_GATHER]]
-; CHECK-NEXT: [[TMP12]] = add <vscale x 4 x i32> [[VEC_PHI1]], [[WIDE_MASKED_GATHER2]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 [[TMP8]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i64 [[TMP9]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4
+; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 4 x i32>, ptr [[TMP10]], align 4
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x i32>, ptr [[TMP11]], align 4
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <vscale x 4 x i32>, ptr [[TMP12]], align 4
+; CHECK-NEXT: [[TMP13]] = add <vscale x 4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP14]] = add <vscale x 4 x i32> [[VEC_PHI1]], [[WIDE_LOAD4]]
; CHECK-NEXT: [[TMP15]] = add <vscale x 4 x i32> [[VEC_PHI2]], [[WIDE_LOAD5]]
; CHECK-NEXT: [[TMP16]] = add <vscale x 4 x i32> [[VEC_PHI3]], [[WIDE_LOAD6]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]]
-; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
+; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <vscale x 4 x i32> [[TMP12]], [[TMP11]]
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <vscale x 4 x i32> [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <vscale x 4 x i32> [[TMP15]], [[BIN_RDX]]
; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <vscale x 4 x i32> [[TMP16]], [[BIN_RDX7]]
; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[BIN_RDX8]])
@@ -484,7 +475,7 @@ define i32 @scalable_vf_rejected(ptr %A, i64 %N) #0 {
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP15:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP18]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i32 [[R]]
@@ -515,3 +506,149 @@ attributes #0 = { vscale_range(1,16) "target-features"="+sve" }
!3 = distinct !{!3, !4, !5}
!4 = !{!"llvm.loop.vectorize.width", i32 4}
!5 = !{!"llvm.loop.interleave.count", i32 8}!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
+
+
+; Loop combining a bounded (i % 4) load with a reverse-stride load.
+define i32 @reverse_load_with_bounded(ptr %A, ptr %B, i32 %N) {
+; CHECK-LABEL: define i32 @reverse_load_with_bounded(
+; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
+; CHECK: [[VECTOR_SCEVCHECK]]:
+; CHECK-NEXT: [[TMP0:%.*]] = icmp sgt i32 1, [[N]]
+; CHECK-NEXT: br i1 [[TMP0]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH1:.*]]
+; CHECK: [[VECTOR_PH1]]:
+; CHECK-NEXT: [[N_MOD_VF1:%.*]] = urem i32 [[N]], 16
+; CHECK-NEXT: [[N_VEC1:%.*]] = sub i32 [[N]], [[N_MOD_VF1]]
+; CHECK-NEXT: br label %[[VECTOR_BODY1:.*]]
+; CHECK: [[VECTOR_BODY1]]:
+; CHECK-NEXT: [[INDEX1:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[TMP29:%.*]] = add i32 [[INDEX1]], 4
+; CHECK-NEXT: [[TMP30:%.*]] = add i32 [[INDEX1]], 8
+; CHECK-NEXT: [[TMP31:%.*]] = add i32 [[INDEX1]], 12
+; CHECK-NEXT: [[TMP32:%.*]] = urem i32 [[INDEX1]], 4
+; CHECK-NEXT: [[TMP33:%.*]] = urem i32 [[TMP29]], 4
+; CHECK-NEXT: [[TMP34:%.*]] = urem i32 [[TMP30]], 4
+; CHECK-NEXT: [[TMP35:%.*]] = urem i32 [[TMP31]], 4
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP32]]
+; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP33]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP34]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP35]]
+; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i32>, ptr [[TMP36]], align 4
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP37]], align 4
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP11]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = sub i32 [[N]], [[INDEX1]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 -3
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 -7
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 -11
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 -15
+; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP14]], align 4
+; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4
+; CHECK-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4
+; CHECK-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i32>, ptr [[TMP17]], align 4
+; CHECK-NEXT: [[REVERSE1:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD8]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[REVERSE12:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD9]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[REVERSE13:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD10]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[REVERSE14:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD11]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[TMP18:%.*]] = add <4 x i32> [[WIDE_LOAD2]], [[REVERSE1]]
+; CHECK-NEXT: [[TMP19:%.*]] = add <4 x i32> [[WIDE_LOAD5]], [[REVERSE12]]
+; CHECK-NEXT: [[TMP20:%.*]] = add <4 x i32> [[WIDE_LOAD6]], [[REVERSE13]]
+; CHECK-NEXT: [[TMP21:%.*]] = add <4 x i32> [[WIDE_LOAD7]], [[REVERSE14]]
+; CHECK-NEXT: [[TMP22]] = add <4 x i32> [[VEC_PHI1]], [[TMP18]]
+; CHECK-NEXT: [[TMP23]] = add <4 x i32> [[VEC_PHI2]], [[TMP19]]
+; CHECK-NEXT: [[TMP24]] = add <4 x i32> [[VEC_PHI3]], [[TMP20]]
+; CHECK-NEXT: [[TMP25]] = add <4 x i32> [[VEC_PHI4]], [[TMP21]]
+; CHECK-NEXT: [[INDEX_NEXT1]] = add nuw i32 [[INDEX1]], 16
+; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i32 [[INDEX_NEXT1]], [[N_VEC1]]
+; CHECK-NEXT: br i1 [[TMP26]], label %[[MIDDLE_BLOCK1:.*]], label %[[VECTOR_BODY1]], !llvm.loop [[LOOP15:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK1]]:
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP23]], [[TMP22]]
+; CHECK-NEXT: [[BIN_RDX15:%.*]] = add <4 x i32> [[TMP24]], [[BIN_RDX]]
+; CHECK-NEXT: [[BIN_RDX16:%.*]] = add <4 x i32> [[TMP25]], [[BIN_RDX15]]
+; CHECK-NEXT: [[TMP27:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX16]])
+; CHECK-NEXT: [[CMP_N1:%.*]] = icmp eq i32 [[N]], [[N_VEC1]]
+; CHECK-NEXT: br i1 [[CMP_N1]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
+; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
+; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF1]], 4
+; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF5]]
+; CHECK: [[VEC_EPILOG_PH]]:
+; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC1]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP27]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <4 x i32> zeroinitializer, i32 [[BC_MERGE_RDX]], i32 0
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ [[TMP28]], %[[VEC_EPILOG_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = urem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP1]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[N]], [[INDEX]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 -3
+; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD1]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[TMP6:%.*]] = add <4 x i32> [[WIDE_LOAD]], [[REVERSE]]
+; CHECK-NEXT: [[TMP7]] = add <4 x i32> [[VEC_PHI]], [[TMP6]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]])
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ [[N_VEC1]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX26:%.*]] = phi i32 [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ [[TMP27]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX26]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
+; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
+; CHECK-NEXT: [[LV1:%.*]] = load i32, ptr [[GEP1]], align 4
+; CHECK-NEXT: [[REV_IDX:%.*]] = sub i32 [[N]], [[IV]]
+; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[REV_IDX]]
+; CHECK-NEXT: [[LV2:%.*]] = load i32, ptr [[GEP2]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[LV1]], [[LV2]]
+; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[ADD]]
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP27]], %[[MIDDLE_BLOCK1]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: ret i32 [[R]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
+ %sum = phi i32 [ 0, %entry ], [ %sum.next, %loop ]
+ %bounded = urem i32 %iv, 4
+ %gep1 = getelementptr inbounds i32, ptr %A, i32 %bounded
+ %lv1 = load i32, ptr %gep1
+ %rev_idx = sub i32 %N, %iv
+ %gep2 = getelementptr inbounds i32, ptr %B, i32 %rev_idx
+ %lv2 = load i32, ptr %gep2
+ %add = add i32 %lv1, %lv2
+ %sum.next = add i32 %sum, %add
+ %iv.next = add nuw nsw i32 %iv, 1
+ %cond = icmp eq i32 %iv.next, %N
+ br i1 %cond, label %exit, label %loop
+
+exit:
+ %r = phi i32 [ %sum.next, %loop ]
+ ret i32 %r
+}
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll b/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll
index 8f4bbfc66d778..9d725921ae197 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll
@@ -15,17 +15,13 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 127
-; CHECK-NEXT: br i1 [[TMP3]], label %[[SCALAR_PH]], label %[[VECTOR_PH1:.*]]
-; CHECK: [[VECTOR_PH1]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]
-; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH1]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP4:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
; CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[VEC_IND]], splat (i32 1)
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[TMP0]], zeroinitializer
; CHECK-NEXT: [[TMP28:%.*]] = urem <4 x i32> [[VEC_IND]], splat (i32 128)
@@ -80,8 +76,8 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -110,20 +106,16 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 16
; IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC4: [[VECTOR_PH]]:
-; IC4-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC4-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 127
-; IC4-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH1:.*]]
-; IC4: [[VECTOR_PH1]]:
; IC4-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
; IC4-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; IC4-NEXT: br label %[[VECTOR_BODY:.*]]
; IC4: [[VECTOR_BODY]]:
-; IC4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33:.*]] ]
-; IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH1]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP19:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP23:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[TMP20:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP21:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP25:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33:.*]] ]
+; IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[TMP20:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
; IC4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i32> [[VEC_IND]], splat (i32 4)
; IC4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i32> [[STEP_ADD]], splat (i32 4)
; IC4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i32> [[STEP_ADD_2]], splat (i32 4)
@@ -319,8 +311,8 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC4-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC4: [[SCALAR_PH]]:
-; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
-; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP24]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
+; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP24]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC4-NEXT: br label %[[LOOP:.*]]
; IC4: [[LOOP]]:
; IC4-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -349,24 +341,20 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC8-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 32
; IC8-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC8: [[VECTOR_PH]]:
-; IC8-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC8-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 127
-; IC8-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH1:.*]]
-; IC8: [[VECTOR_PH1]]:
; IC8-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 32
; IC8-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; IC8-NEXT: br label %[[VECTOR_BODY:.*]]
; IC8: [[VECTOR_BODY]]:
-; IC8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69:.*]] ]
-; IC8-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH1]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP39:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP40:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP41:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP42:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP43:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP44:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP45:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP46:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69:.*]] ]
+; IC8-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP39:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP40:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP41:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP42:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP43:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP44:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP45:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP46:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
; IC8-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i32> [[VEC_IND]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i32> [[STEP_ADD]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i32> [[STEP_ADD_2]], splat (i32 4)
@@ -750,8 +738,8 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC8-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC8-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC8: [[SCALAR_PH]]:
-; IC8-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
-; IC8-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP48]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
+; IC8-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC8-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP48]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC8-NEXT: br label %[[LOOP:.*]]
; IC8: [[LOOP]]:
; IC8-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -816,17 +804,13 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 15
-; CHECK-NEXT: br i1 [[TMP3]], label %[[SCALAR_PH]], label %[[VECTOR_PH1:.*]]
-; CHECK: [[VECTOR_PH1]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]
-; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH1]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP4:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
; CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[VEC_IND]], splat (i32 1)
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[TMP0]], zeroinitializer
; CHECK-NEXT: [[TMP28:%.*]] = urem <4 x i32> [[VEC_IND]], splat (i32 16)
@@ -881,8 +865,8 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -911,20 +895,16 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 16
; IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC4: [[VECTOR_PH]]:
-; IC4-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC4-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 15
-; IC4-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH1:.*]]
-; IC4: [[VECTOR_PH1]]:
; IC4-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
; IC4-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; IC4-NEXT: br label %[[VECTOR_BODY:.*]]
; IC4: [[VECTOR_BODY]]:
-; IC4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33:.*]] ]
-; IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH1]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP19:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP20:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP21:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP22:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33:.*]] ]
+; IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
; IC4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i32> [[VEC_IND]], splat (i32 4)
; IC4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i32> [[STEP_ADD]], splat (i32 4)
; IC4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i32> [[STEP_ADD_2]], splat (i32 4)
@@ -1120,8 +1100,8 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC4-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC4: [[SCALAR_PH]]:
-; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
-; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP24]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
+; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP24]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC4-NEXT: br label %[[LOOP:.*]]
; IC4: [[LOOP]]:
; IC4-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -1150,24 +1130,20 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC8-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 32
; IC8-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC8: [[VECTOR_PH]]:
-; IC8-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC8-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 15
-; IC8-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH1:.*]]
-; IC8: [[VECTOR_PH1]]:
; IC8-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 32
; IC8-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; IC8-NEXT: br label %[[VECTOR_BODY:.*]]
; IC8: [[VECTOR_BODY]]:
-; IC8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69:.*]] ]
-; IC8-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH1]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP19:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP20:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP21:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP22:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP222:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP223:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP224:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP225:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69:.*]] ]
+; IC8-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP222:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP223:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP224:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP225:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
; IC8-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i32> [[VEC_IND]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i32> [[STEP_ADD]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i32> [[STEP_ADD_2]], splat (i32 4)
@@ -1551,8 +1527,8 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC8-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC8-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC8: [[SCALAR_PH]]:
-; IC8-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
-; IC8-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP227]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_PH]] ]
+; IC8-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC8-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP227]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC8-NEXT: br label %[[LOOP:.*]]
; IC8: [[LOOP]]:
; IC8-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -1605,21 +1581,21 @@ exit:
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
;.
; IC4: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; IC4: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; IC4: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+; IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
; IC4: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; IC4: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; IC4: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
;.
; IC8: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; IC8: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; IC8: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; IC8: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+; IC8: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
; IC8: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; IC8: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; IC8: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
;.
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load-user-ic.ll b/llvm/test/Transforms/LoopVectorize/bounded-load-user-ic.ll
index 01699dcdce89e..1cb7f155fbfbb 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load-user-ic.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load-user-ic.ll
@@ -1,68 +1,136 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
-; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=3 -S %s | FileCheck %s
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=4 -S %s | FileCheck %s --check-prefix=IC4
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=3 -S %s | FileCheck %s --check-prefix=IC3
-define i32 @bounded_user_ic_capped_to_divisor(ptr %A, i32 %N) {
-; CHECK-LABEL: define i32 @bounded_user_ic_capped_to_divisor(
-; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 12
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 127
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 12
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
-; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
-; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[INDEX]], 128
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 4
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 8
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4
-; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4
-; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
-; CHECK-NEXT: [[TMP6]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP7]] = add <4 x i32> [[VEC_PHI1]], [[WIDE_LOAD3]]
-; CHECK-NEXT: [[TMP8]] = add <4 x i32> [[VEC_PHI2]], [[WIDE_LOAD4]]
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 12
-; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP7]], [[TMP6]]
-; CHECK-NEXT: [[BIN_RDX5:%.*]] = add <4 x i32> [[TMP8]], [[BIN_RDX]]
-; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX5]])
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
-; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: br label %[[LOOP:.*]]
-; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 128
-; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
-; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: ret i32 [[R]]
+; A user-forced interleave count is honored in full for bounded (i % 2^N) loads,
+; even when VF * IC exceeds the window (here VF=4, IC=4, window=8 => VF*IC=16).
+; This is safe without a cap: each unrolled part re-derives its address as
+; A[(i + Part * VF) % 8], which is a multiple of VF in [0, 8), so no part ever
+; reads past the window regardless of the interleave count.
+define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
+; IC4-LABEL: define i32 @bounded_user_ic_exceeds_window(
+; IC4-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
+; IC4-NEXT: [[ENTRY:.*]]:
+; IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 16
+; IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; IC4: [[VECTOR_PH]]:
+; IC4-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
+; IC4-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
+; IC4-NEXT: br label %[[VECTOR_BODY:.*]]
+; IC4: [[VECTOR_BODY]]:
+; IC4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; IC4-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; IC4-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 12
+; IC4-NEXT: [[TMP3:%.*]] = urem i32 [[INDEX]], 8
+; IC4-NEXT: [[TMP4:%.*]] = urem i32 [[TMP0]], 8
+; IC4-NEXT: [[TMP5:%.*]] = urem i32 [[TMP1]], 8
+; IC4-NEXT: [[TMP6:%.*]] = urem i32 [[TMP2]], 8
+; IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP3]]
+; IC4-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP4]]
+; IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP5]]
+; IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP6]]
+; IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4
+; IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP8]], align 4
+; IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4
+; IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP14]], align 4
+; IC4-NEXT: [[TMP9]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; IC4-NEXT: [[TMP10]] = add <4 x i32> [[VEC_PHI1]], [[WIDE_LOAD4]]
+; IC4-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI2]], [[WIDE_LOAD5]]
+; IC4-NEXT: [[TMP12]] = add <4 x i32> [[VEC_PHI3]], [[WIDE_LOAD6]]
+; IC4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
+; IC4-NEXT: [[TMP15:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; IC4-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; IC4: [[MIDDLE_BLOCK]]:
+; IC4-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP10]], [[TMP9]]
+; IC4-NEXT: [[BIN_RDX7:%.*]] = add <4 x i32> [[TMP11]], [[BIN_RDX]]
+; IC4-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP12]], [[BIN_RDX7]]
+; IC4-NEXT: [[TMP16:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX8]])
+; IC4-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
+; IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; IC4: [[SCALAR_PH]]:
+; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP16]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC4-NEXT: br label %[[LOOP:.*]]
+; IC4: [[LOOP]]:
+; IC4-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; IC4-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; IC4-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
+; IC4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
+; IC4-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
+; IC4-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
+; IC4-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; IC4-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
+; IC4-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; IC4: [[EXIT]]:
+; IC4-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP16]], %[[MIDDLE_BLOCK]] ]
+; IC4-NEXT: ret i32 [[R]]
+;
+; IC3-LABEL: define i32 @bounded_user_ic_exceeds_window(
+; IC3-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
+; IC3-NEXT: [[ENTRY:.*]]:
+; IC3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 12
+; IC3-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; IC3: [[VECTOR_PH]]:
+; IC3-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 12
+; IC3-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
+; IC3-NEXT: br label %[[VECTOR_BODY:.*]]
+; IC3: [[VECTOR_BODY]]:
+; IC3-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC3-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; IC3-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
+; IC3-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; IC3-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; IC3-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; IC3-NEXT: [[TMP2:%.*]] = urem i32 [[INDEX]], 8
+; IC3-NEXT: [[TMP3:%.*]] = urem i32 [[TMP0]], 8
+; IC3-NEXT: [[TMP4:%.*]] = urem i32 [[TMP1]], 8
+; IC3-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
+; IC3-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP3]]
+; IC3-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP4]]
+; IC3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
+; IC3-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4
+; IC3-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4
+; IC3-NEXT: [[TMP7]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; IC3-NEXT: [[TMP8]] = add <4 x i32> [[VEC_PHI1]], [[WIDE_LOAD3]]
+; IC3-NEXT: [[TMP9]] = add <4 x i32> [[VEC_PHI2]], [[WIDE_LOAD4]]
+; IC3-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 12
+; IC3-NEXT: [[TMP11:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; IC3-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; IC3: [[MIDDLE_BLOCK]]:
+; IC3-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP8]], [[TMP7]]
+; IC3-NEXT: [[BIN_RDX5:%.*]] = add <4 x i32> [[TMP9]], [[BIN_RDX]]
+; IC3-NEXT: [[TMP12:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX5]])
+; IC3-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
+; IC3-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; IC3: [[SCALAR_PH]]:
+; IC3-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC3-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP12]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC3-NEXT: br label %[[LOOP:.*]]
+; IC3: [[LOOP]]:
+; IC3-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; IC3-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; IC3-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
+; IC3-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
+; IC3-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
+; IC3-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
+; IC3-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; IC3-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
+; IC3-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; IC3: [[EXIT]]:
+; IC3-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP12]], %[[MIDDLE_BLOCK]] ]
+; IC3-NEXT: ret i32 [[R]]
;
entry:
br label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
%sum = phi i32 [ 0, %entry ], [ %sum.next, %loop ]
- %bounded = urem i32 %iv, 128
+ %bounded = urem i32 %iv, 8
%gep.A = getelementptr inbounds i32, ptr %A, i32 %bounded
%lv = load i32, ptr %gep.A, align 4
%sum.next = add i32 %sum, %lv
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load-vf-ranges.ll b/llvm/test/Transforms/LoopVectorize/bounded-load-vf-ranges.ll
index adeed75278ba6..d8e0998a1c4d4 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load-vf-ranges.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load-vf-ranges.ll
@@ -6,57 +6,101 @@
define i32 @bounded_load_reduction_bound4(ptr %A) {
; VF2-LABEL: define i32 @bounded_load_reduction_bound4(
; VF2-SAME: ptr [[A:%.*]]) {
-; VF2-NEXT: [[ENTRY:.*]]:
-; VF2-NEXT: br label %[[LOOP:.*]]
-; VF2: [[LOOP]]:
-; VF2-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
-; VF2-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF2-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF2-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF2-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF2-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF2-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF2-NEXT: [[ENTRY:.*:]]
+; VF2-NEXT: br label %[[VECTOR_PH:.*]]
+; VF2: [[VECTOR_PH]]:
+; VF2-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF2: [[VECTOR_BODY]]:
+; VF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 4
+; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4
+; VF2-NEXT: [[TMP2]] = add <2 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
+; VF2-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF2-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF2: [[MIDDLE_BLOCK]]:
+; VF2-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP2]])
+; VF2-NEXT: br label %[[EXIT:.*]]
; VF2: [[EXIT]]:
-; VF2-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF2-NEXT: ret i32 [[R]]
+; VF2-NEXT: ret i32 [[TMP4]]
;
; VF4-LABEL: define i32 @bounded_load_reduction_bound4(
; VF4-SAME: ptr [[A:%.*]]) {
-; VF4-NEXT: [[ENTRY:.*]]:
-; VF4-NEXT: br label %[[LOOP:.*]]
-; VF4: [[LOOP]]:
-; VF4-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
-; VF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF4-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF4-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF4-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF4-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF4-NEXT: [[ENTRY:.*:]]
+; VF4-NEXT: br label %[[VECTOR_PH:.*]]
+; VF4: [[VECTOR_PH]]:
+; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF4: [[VECTOR_BODY]]:
+; VF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 4
+; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
+; VF4-NEXT: [[TMP2]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; VF4-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF4-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF4: [[MIDDLE_BLOCK]]:
+; VF4-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
+; VF4-NEXT: br label %[[EXIT:.*]]
; VF4: [[EXIT]]:
-; VF4-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF4-NEXT: ret i32 [[R]]
+; VF4-NEXT: ret i32 [[TMP4]]
;
; VF8-LABEL: define i32 @bounded_load_reduction_bound4(
; VF8-SAME: ptr [[A:%.*]]) {
-; VF8-NEXT: [[ENTRY:.*]]:
-; VF8-NEXT: br label %[[LOOP:.*]]
-; VF8: [[LOOP]]:
-; VF8-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
-; VF8-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF8-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF8-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF8-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF8-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF8-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF8-NEXT: [[ENTRY:.*:]]
+; VF8-NEXT: br label %[[VECTOR_PH:.*]]
+; VF8: [[VECTOR_PH]]:
+; VF8-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF8: [[VECTOR_BODY]]:
+; VF8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP33:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[TMP0:%.*]] = urem <8 x i32> [[VEC_IND]], splat (i32 4)
+; VF8-NEXT: [[TMP1:%.*]] = extractelement <8 x i32> [[TMP0]], i64 0
+; VF8-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP1]]
+; VF8-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[TMP0]], i64 1
+; VF8-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
+; VF8-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP0]], i64 2
+; VF8-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP3]]
+; VF8-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP0]], i64 3
+; VF8-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP4]]
+; VF8-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP0]], i64 4
+; VF8-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP5]]
+; VF8-NEXT: [[TMP6:%.*]] = extractelement <8 x i32> [[TMP0]], i64 5
+; VF8-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP6]]
+; VF8-NEXT: [[TMP7:%.*]] = extractelement <8 x i32> [[TMP0]], i64 6
+; VF8-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP7]]
+; VF8-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP0]], i64 7
+; VF8-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP8]]
+; VF8-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP9]], align 4
+; VF8-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP10]], align 4
+; VF8-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP11]], align 4
+; VF8-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP12]], align 4
+; VF8-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP13]], align 4
+; VF8-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP14]], align 4
+; VF8-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP15]], align 4
+; VF8-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP16]], align 4
+; VF8-NEXT: [[TMP25:%.*]] = insertelement <8 x i32> poison, i32 [[TMP17]], i32 0
+; VF8-NEXT: [[TMP26:%.*]] = insertelement <8 x i32> [[TMP25]], i32 [[TMP18]], i32 1
+; VF8-NEXT: [[TMP27:%.*]] = insertelement <8 x i32> [[TMP26]], i32 [[TMP19]], i32 2
+; VF8-NEXT: [[TMP28:%.*]] = insertelement <8 x i32> [[TMP27]], i32 [[TMP20]], i32 3
+; VF8-NEXT: [[TMP29:%.*]] = insertelement <8 x i32> [[TMP28]], i32 [[TMP21]], i32 4
+; VF8-NEXT: [[TMP30:%.*]] = insertelement <8 x i32> [[TMP29]], i32 [[TMP22]], i32 5
+; VF8-NEXT: [[TMP31:%.*]] = insertelement <8 x i32> [[TMP30]], i32 [[TMP23]], i32 6
+; VF8-NEXT: [[TMP32:%.*]] = insertelement <8 x i32> [[TMP31]], i32 [[TMP24]], i32 7
+; VF8-NEXT: [[TMP33]] = add <8 x i32> [[VEC_PHI]], [[TMP32]]
+; VF8-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; VF8-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <8 x i32> [[VEC_IND]], splat (i32 8)
+; VF8-NEXT: [[TMP34:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF8-NEXT: br i1 [[TMP34]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF8: [[MIDDLE_BLOCK]]:
+; VF8-NEXT: [[TMP35:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP33]])
+; VF8-NEXT: br label %[[EXIT:.*]]
; VF8: [[EXIT]]:
-; VF8-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF8-NEXT: ret i32 [[R]]
+; VF8-NEXT: ret i32 [[TMP35]]
;
entry:
br label %loop
@@ -80,57 +124,69 @@ exit:
define i32 @bounded_load_reduction_bound8(ptr %A) {
; VF2-LABEL: define i32 @bounded_load_reduction_bound8(
; VF2-SAME: ptr [[A:%.*]]) {
-; VF2-NEXT: [[ENTRY:.*]]:
-; VF2-NEXT: br label %[[LOOP:.*]]
-; VF2: [[LOOP]]:
-; VF2-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF2-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF2-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF2-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF2-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF2-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF2-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF2-NEXT: [[ENTRY:.*:]]
+; VF2-NEXT: br label %[[VECTOR_PH:.*]]
+; VF2: [[VECTOR_PH]]:
+; VF2-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF2: [[VECTOR_BODY]]:
+; VF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4
+; VF2-NEXT: [[TMP2]] = add <2 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
+; VF2-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF2-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF2: [[MIDDLE_BLOCK]]:
+; VF2-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP2]])
+; VF2-NEXT: br label %[[EXIT:.*]]
; VF2: [[EXIT]]:
-; VF2-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF2-NEXT: ret i32 [[R]]
+; VF2-NEXT: ret i32 [[TMP4]]
;
; VF4-LABEL: define i32 @bounded_load_reduction_bound8(
; VF4-SAME: ptr [[A:%.*]]) {
-; VF4-NEXT: [[ENTRY:.*]]:
-; VF4-NEXT: br label %[[LOOP:.*]]
-; VF4: [[LOOP]]:
-; VF4-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF4-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF4-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF4-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF4-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF4-NEXT: [[ENTRY:.*:]]
+; VF4-NEXT: br label %[[VECTOR_PH:.*]]
+; VF4: [[VECTOR_PH]]:
+; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF4: [[VECTOR_BODY]]:
+; VF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
+; VF4-NEXT: [[TMP2]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; VF4-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF4-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF4: [[MIDDLE_BLOCK]]:
+; VF4-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
+; VF4-NEXT: br label %[[EXIT:.*]]
; VF4: [[EXIT]]:
-; VF4-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF4-NEXT: ret i32 [[R]]
+; VF4-NEXT: ret i32 [[TMP4]]
;
; VF8-LABEL: define i32 @bounded_load_reduction_bound8(
; VF8-SAME: ptr [[A:%.*]]) {
-; VF8-NEXT: [[ENTRY:.*]]:
-; VF8-NEXT: br label %[[LOOP:.*]]
-; VF8: [[LOOP]]:
-; VF8-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF8-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF8-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF8-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF8-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF8-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF8-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF8-NEXT: [[ENTRY:.*:]]
+; VF8-NEXT: br label %[[VECTOR_PH:.*]]
+; VF8: [[VECTOR_PH]]:
+; VF8-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF8: [[VECTOR_BODY]]:
+; VF8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF8-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF8-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[TMP1]], align 4
+; VF8-NEXT: [[TMP2]] = add <8 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF8-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; VF8-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF8-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF8: [[MIDDLE_BLOCK]]:
+; VF8-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP2]])
+; VF8-NEXT: br label %[[EXIT:.*]]
; VF8: [[EXIT]]:
-; VF8-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF8-NEXT: ret i32 [[R]]
+; VF8-NEXT: ret i32 [[TMP4]]
;
entry:
br label %loop
@@ -154,60 +210,72 @@ exit:
define i32 @bounded_load_reduction_bound8_i8(ptr %A) {
; VF2-LABEL: define i32 @bounded_load_reduction_bound8_i8(
; VF2-SAME: ptr [[A:%.*]]) {
-; VF2-NEXT: [[ENTRY:.*]]:
-; VF2-NEXT: br label %[[LOOP:.*]]
-; VF2: [[LOOP]]:
-; VF2-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF2-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[BOUNDED]]
-; VF2-NEXT: [[LV:%.*]] = load i8, ptr [[GEP_A]], align 1
-; VF2-NEXT: [[EXT:%.*]] = zext i8 [[LV]] to i32
-; VF2-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[EXT]]
-; VF2-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF2-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF2-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF2-NEXT: [[ENTRY:.*:]]
+; VF2-NEXT: br label %[[VECTOR_PH:.*]]
+; VF2: [[VECTOR_PH]]:
+; VF2-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF2: [[VECTOR_BODY]]:
+; VF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[TMP0]]
+; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP1]], align 1
+; VF2-NEXT: [[TMP2:%.*]] = zext <2 x i8> [[WIDE_LOAD]] to <2 x i32>
+; VF2-NEXT: [[TMP3]] = add <2 x i32> [[VEC_PHI]], [[TMP2]]
+; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
+; VF2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF2-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; VF2: [[MIDDLE_BLOCK]]:
+; VF2-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP3]])
+; VF2-NEXT: br label %[[EXIT:.*]]
; VF2: [[EXIT]]:
-; VF2-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF2-NEXT: ret i32 [[R]]
+; VF2-NEXT: ret i32 [[TMP5]]
;
; VF4-LABEL: define i32 @bounded_load_reduction_bound8_i8(
; VF4-SAME: ptr [[A:%.*]]) {
-; VF4-NEXT: [[ENTRY:.*]]:
-; VF4-NEXT: br label %[[LOOP:.*]]
-; VF4: [[LOOP]]:
-; VF4-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[BOUNDED]]
-; VF4-NEXT: [[LV:%.*]] = load i8, ptr [[GEP_A]], align 1
-; VF4-NEXT: [[EXT:%.*]] = zext i8 [[LV]] to i32
-; VF4-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[EXT]]
-; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF4-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF4-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF4-NEXT: [[ENTRY:.*:]]
+; VF4-NEXT: br label %[[VECTOR_PH:.*]]
+; VF4: [[VECTOR_PH]]:
+; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF4: [[VECTOR_BODY]]:
+; VF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[TMP0]]
+; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1
+; VF4-NEXT: [[TMP2:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>
+; VF4-NEXT: [[TMP3]] = add <4 x i32> [[VEC_PHI]], [[TMP2]]
+; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; VF4-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF4-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; VF4: [[MIDDLE_BLOCK]]:
+; VF4-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])
+; VF4-NEXT: br label %[[EXIT:.*]]
; VF4: [[EXIT]]:
-; VF4-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF4-NEXT: ret i32 [[R]]
+; VF4-NEXT: ret i32 [[TMP5]]
;
; VF8-LABEL: define i32 @bounded_load_reduction_bound8_i8(
; VF8-SAME: ptr [[A:%.*]]) {
-; VF8-NEXT: [[ENTRY:.*]]:
-; VF8-NEXT: br label %[[LOOP:.*]]
-; VF8: [[LOOP]]:
-; VF8-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF8-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[BOUNDED]]
-; VF8-NEXT: [[LV:%.*]] = load i8, ptr [[GEP_A]], align 1
-; VF8-NEXT: [[EXT:%.*]] = zext i8 [[LV]] to i32
-; VF8-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[EXT]]
-; VF8-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF8-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF8-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF8-NEXT: [[ENTRY:.*:]]
+; VF8-NEXT: br label %[[VECTOR_PH:.*]]
+; VF8: [[VECTOR_PH]]:
+; VF8-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF8: [[VECTOR_BODY]]:
+; VF8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF8-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[TMP0]]
+; VF8-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP1]], align 1
+; VF8-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
+; VF8-NEXT: [[TMP3]] = add <8 x i32> [[VEC_PHI]], [[TMP2]]
+; VF8-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; VF8-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF8-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; VF8: [[MIDDLE_BLOCK]]:
+; VF8-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP3]])
+; VF8-NEXT: br label %[[EXIT:.*]]
; VF8: [[EXIT]]:
-; VF8-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF8-NEXT: ret i32 [[R]]
+; VF8-NEXT: ret i32 [[TMP5]]
;
entry:
br label %loop
@@ -257,7 +325,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF2-NEXT: store <2 x i32> [[TMP5]], ptr [[TMP3]], align 4
; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
; VF2-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; VF2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; VF2: [[MIDDLE_BLOCK]]:
; VF2-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; VF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
@@ -275,7 +343,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF2-NEXT: store i32 [[SUM]], ptr [[GEP_A]], align 4
; VF2-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; VF2-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; VF2-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF2-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; VF2: [[EXIT]]:
; VF2-NEXT: ret void
;
@@ -303,7 +371,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF4-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP3]], align 4
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; VF4-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; VF4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; VF4: [[MIDDLE_BLOCK]]:
; VF4-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; VF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
@@ -321,7 +389,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF4-NEXT: store i32 [[SUM]], ptr [[GEP_A]], align 4
; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; VF4-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; VF4-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF4-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; VF4: [[EXIT]]:
; VF4-NEXT: ret void
;
@@ -349,7 +417,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF8-NEXT: store <8 x i32> [[TMP5]], ptr [[TMP3]], align 4
; VF8-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
; VF8-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; VF8-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF8-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; VF8: [[MIDDLE_BLOCK]]:
; VF8-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; VF8-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
@@ -367,7 +435,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF8-NEXT: store i32 [[SUM]], ptr [[GEP_A]], align 4
; VF8-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; VF8-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; VF8-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF8-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; VF8: [[EXIT]]:
; VF8-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load.ll b/llvm/test/Transforms/LoopVectorize/bounded-load.ll
index f64ba1046b60a..9bb5faf3e769a 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load.ll
@@ -6,21 +6,41 @@ target datalayout = "e-m:o-p:64:64-p1:128:128-n8:16:32:64-S128"
define i24 @bounded_load_i24_alloc_size(ptr %A) {
; CHECK-LABEL: define i24 @bounded_load_i24_alloc_size(
; CHECK-SAME: ptr [[A:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: br label %[[LOOP:.*]]
-; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i24 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[BOUNDED:%.*]] = urem i64 [[IV]], 4
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[BOUNDED]]
-; CHECK-NEXT: [[LV:%.*]] = load i24, ptr [[GEP]], align 4
-; CHECK-NEXT: [[SUM_NEXT]] = add i24 [[SUM]], [[LV]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IV_NEXT]], 128
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i24> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = urem <4 x i64> [[VEC_IND]], splat (i64 4)
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i64> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[TMP2]]
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[TMP3]]
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i64> [[TMP0]], i64 3
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP9:%.*]] = load i24, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i24, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = load i24, ptr [[TMP7]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = load i24, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i24> poison, i24 [[TMP9]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i24> [[TMP13]], i24 [[TMP10]], i32 1
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i24> [[TMP14]], i24 [[TMP11]], i32 2
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i24> [[TMP15]], i24 [[TMP12]], i32 3
+; CHECK-NEXT: [[TMP17]] = add <4 x i24> [[VEC_PHI]], [[TMP16]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
+; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
+; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP19:%.*]] = call i24 @llvm.vector.reduce.add.v4i24(<4 x i24> [[TMP17]])
+; CHECK-NEXT: br label %[[EXIT:.*]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i24 [ [[SUM_NEXT]], %[[LOOP]] ]
-; CHECK-NEXT: ret i24 [[SUM_NEXT_LCSSA]]
+; CHECK-NEXT: ret i24 [[TMP19]]
;
entry:
br label %loop
@@ -72,7 +92,7 @@ define i32 @bounded_load_non_pow2_modulus(ptr %A) {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 4)
; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
-; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP19:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP17]])
; CHECK-NEXT: br label %[[EXIT:.*]]
@@ -141,21 +161,25 @@ exit:
define i32 @bounded_load_srem_nonneg(ptr %A) {
; CHECK-LABEL: define i32 @bounded_load_srem_nonneg(
; CHECK-SAME: ptr [[A:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: br label %[[LOOP:.*]]
-; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[BOUNDED:%.*]] = srem i32 [[IV]], 4
-; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = srem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
+; CHECK-NEXT: [[TMP2]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
+; CHECK-NEXT: br label %[[EXIT:.*]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; CHECK-NEXT: ret i32 [[R]]
+; CHECK-NEXT: ret i32 [[TMP4]]
;
entry:
br label %loop
@@ -211,7 +235,7 @@ define i32 @bounded_load_srem_maybe_negative(ptr %A, i32 %n) {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 4)
; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
-; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP20:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP18]])
; CHECK-NEXT: br label %[[EXIT:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check-small-bounded-ranges.ll b/llvm/test/Transforms/LoopVectorize/runtime-check-small-bounded-ranges.ll
index 7d50d1a4673f2..c24ec5c46871b 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-check-small-bounded-ranges.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-check-small-bounded-ranges.ll
@@ -90,11 +90,7 @@ define i32 @bounded_load_reduction(ptr %A, i32 %N) {
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -114,8 +110,8 @@ define i32 @bounded_load_reduction(ptr %A, i32 %N) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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