[llvm] [LLVM][CodeGen][SVE] Lower to multivector stores (PR #207397)

[Sander de Smalen via llvm-commits]

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@@ -16,33 +16,33 @@ define void @load_2x_vectors_i8_r(ptr %addr) {
 ; SVE2p1-NEXT:    str z1, [x0]
 ; SVE2p1-NEXT:    ret
 ;
-; SVE2p1-SL-LABEL: load_2x_vectors_i8_r:
+; SVE2p1-SL-LABEL: load_store_2x_vectors_i8_r:
 ; SVE2p1-SL:       // %bb.0:
 ; SVE2p1-SL-NEXT:    ptrue pn8.b
 ; SVE2p1-SL-NEXT:    ld1b { z0.b, z1.b }, pn8/z, [x0]
 ; SVE2p1-SL-NEXT:    add z1.b, z1.b, #5 // =0x5
 ; SVE2p1-SL-NEXT:    add z0.b, z0.b, #5 // =0x5
-; SVE2p1-SL-NEXT:    str z1, [x0, #1, mul vl]
-; SVE2p1-SL-NEXT:    str z0, [x0]
+; SVE2p1-SL-NEXT:    st1b { z0.b, z1.b }, pn8, [x0]
 ; SVE2p1-SL-NEXT:    ret
 ;
-; SME2-LABEL: load_2x_vectors_i8_r:
+; SME2-LABEL: load_store_2x_vectors_i8_r:
 ; SME2:       // %bb.0:
 ; SME2-NEXT:    ptrue pn8.b
 ; SME2-NEXT:    ld1b { z16.b, z24.b }, pn8/z, [x0]
-; SME2-NEXT:    add z24.b, z24.b, #5 // =0x5
-; SME2-NEXT:    add z16.b, z16.b, #5 // =0x5
-; SME2-NEXT:    str z24, [x0, #1, mul vl]
-; SME2-NEXT:    str z16, [x0]
+; SME2-NEXT:    movprfx z1, z24
+; SME2-NEXT:    add z1.b, z1.b, #5 // =0x5
+; SME2-NEXT:    movprfx z0, z16
+; SME2-NEXT:    add z0.b, z0.b, #5 // =0x5
+; SME2-NEXT:    st1b { z0.b, z1.b }, pn8, [x0]
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sdesmalen-arm wrote:

Yeah that looks like quite a bit of churn. We can add the current functionality under an option (exercised by the tests), but otherwise disabled by default, and then remove the option when register allocation has improved.

https://github.com/llvm/llvm-project/pull/207397