[llvm] afac946 - [GlobalISel] Fix crash in matchCombineInsertVecElts with INLINEASM-de… (#208225)

[via llvm-commits]

Author: Mateusz Chudyk
Date: 2026-07-14T08:36:15Z
New Revision: afac9463c13d6e44f287ee693309497cb79e1e10

URL: https://github.com/llvm/llvm-project/commit/afac9463c13d6e44f287ee693309497cb79e1e10
DIFF: https://github.com/llvm/llvm-project/commit/afac9463c13d6e44f287ee693309497cb79e1e10.diff

LOG: [GlobalISel] Fix crash in matchCombineInsertVecElts with INLINEASM-de… (#208225)

…fined base

matchCombineInsertVecElts walks the G_INSERT_VECTOR_ELT chain by
following operand 0 of the source-defining instruction. When the base
vector is defined by INLINEASM, operand 0 is the asm string (not a
register), so calling getReg() triggers an assertion:

  Assertion `isReg() && "This is not a register operand!"' failed.

Fix by using the mi_match overload that takes a MachineInstr instead of
a Register, which checks the instruction opcode before accessing any
operands.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 072f194b36d5a..b1a1f6de79c61 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -3225,7 +3225,7 @@ bool CombinerHelper::matchCombineInsertVecElts(
   Register TmpReg;
   MatchInfo.resize(NumElts);
   while (mi_match(
-      CurrInst->getOperand(0).getReg(), MRI,
+      *CurrInst, MRI,
       m_GInsertVecElt(m_MInstr(TmpInst), m_Reg(TmpReg), m_ICst(IntImm)))) {
     if (IntImm >= NumElts || IntImm < 0)
       return false;

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
index 86c0575961a17..6584833065484 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir
@@ -311,3 +311,28 @@ body:             |
     RET_ReallyLR
 
 ...
+---
+name:            test_inlineasm_base
+body:             |
+  bb.1:
+    liveins: $x0
+    ; CHECK-LABEL: name: test_inlineasm_base
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[CONST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK-NEXT: [[CONST2:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
+    ; CHECK-NEXT: INLINEASM &"ldr $0, [$1]", sideeffect attdialect, regdef:FPR128, def %3(<4 x s32>), reguse:GPR64, [[DEF]]
+    ; CHECK-NEXT: [[INSERT_VECTOR_ELT:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT %3, [[CONST2]](s32), [[CONST1]](s64)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK-NEXT: G_STORE [[INSERT_VECTOR_ELT]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>))
+    ; CHECK-NEXT: RET_ReallyLR
+    %0:_(s64) = G_CONSTANT i64 0
+    %1:_(s32) = G_CONSTANT i32 42
+    %2:gpr64 = IMPLICIT_DEF
+    INLINEASM &"ldr $0, [$1]", sideeffect attdialect, regdef:FPR128, def %3:fpr128(<4 x s32>), reguse:GPR64, %2:gpr64
+    %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %3:fpr128(<4 x s32>), %1:_(s32), %0:_(s64)
+    %5:_(p0) = COPY $x0
+    G_STORE %4(<4 x s32>), %5(p0) :: (store (<4 x s32>))
+    RET_ReallyLR
+...