[llvm] [ARM] Custom Lower SetCC (PR #193841)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 12:02:13 PDT 2026
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/193841
>From 1428bbfefded7abb48f7d4114dacf41c4abe3603 Mon Sep 17 00:00:00 2001
From: Mike-Goutokuji <gfunni234 at gmail.com>
Date: Wed, 27 May 2026 20:32:46 -0400
Subject: [PATCH 1/2] Modernize tests
This prepares for the next commit
---
llvm/test/CodeGen/ARM/cmp.ll | 195 +++++--
llvm/test/CodeGen/Thumb2/float-cmp.ll | 781 ++++++++++++++++++++------
2 files changed, 756 insertions(+), 220 deletions(-)
diff --git a/llvm/test/CodeGen/ARM/cmp.ll b/llvm/test/CodeGen/ARM/cmp.ll
index 2e6b20cce7323..f2af6c4b631b0 100644
--- a/llvm/test/CodeGen/ARM/cmp.ll
+++ b/llvm/test/CodeGen/ARM/cmp.ll
@@ -1,37 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
define i1 @f1(i32 %a, i32 %b) {
; CHECK-LABEL: f1:
-; CHECK: subs r0, r0, r1
-; CHECK: movwne r0, #1
-; CHECK-T2: subs r0, r0, r1
-; CHECK-T2: it ne
-; CHECK-T2: movne r0, #1
+; CHECK: @ %bb.0:
+; CHECK-NEXT: subs r0, r0, r1
+; CHECK-NEXT: movwne r0, #1
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: f1:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: subs r0, r0, r1
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
%tmp = icmp ne i32 %a, %b
ret i1 %tmp
}
define i1 @f2(i32 %a, i32 %b) {
; CHECK-LABEL: f2:
-; CHECK: sub r0, r0, r1
-; CHECK: clz r0, r0
-; CHECK: lsr r0, r0, #5
-; CHECK-T2: subs r0, r0, r1
-; CHECK-T2: clz r0, r0
-; CHECK-T2: lsrs r0, r0, #5
+; CHECK: @ %bb.0:
+; CHECK-NEXT: sub r0, r0, r1
+; CHECK-NEXT: clz r0, r0
+; CHECK-NEXT: lsr r0, r0, #5
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: f2:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: subs r0, r0, r1
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
%tmp = icmp eq i32 %a, %b
ret i1 %tmp
}
define i1 @f6(i32 %a, i32 %b) {
; CHECK-LABEL: f6:
-; CHECK: sub r0, r0, r1, lsl #5
-; CHECK: clz r0, r0
-; CHECK: lsr r0, r0, #5
-; CHECK-T2: sub.w r0, r0, r1, lsl #5
-; CHECK-T2: clz r0, r0
-; CHECK-T2: lsrs r0, r0, #5
+; CHECK: @ %bb.0:
+; CHECK-NEXT: sub r0, r0, r1, lsl #5
+; CHECK-NEXT: clz r0, r0
+; CHECK-NEXT: lsr r0, r0, #5
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: f6:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: sub.w r0, r0, r1, lsl #5
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
%tmp = shl i32 %b, 5
%tmp1 = icmp eq i32 %a, %tmp
ret i1 %tmp1
@@ -39,11 +58,17 @@ define i1 @f6(i32 %a, i32 %b) {
define i1 @f7(i32 %a, i32 %b) {
; CHECK-LABEL: f7:
-; CHECK: subs r0, r0, r1, lsr #6
-; CHECK: movwne r0, #1
-; CHECK-T2: subs.w r0, r0, r1, lsr #6
-; CHECK-T2: it ne
-; CHECK-T2: movne r0, #1
+; CHECK: @ %bb.0:
+; CHECK-NEXT: subs r0, r0, r1, lsr #6
+; CHECK-NEXT: movwne r0, #1
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: f7:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: subs.w r0, r0, r1, lsr #6
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
%tmp = lshr i32 %b, 6
%tmp1 = icmp ne i32 %a, %tmp
ret i1 %tmp1
@@ -51,12 +76,18 @@ define i1 @f7(i32 %a, i32 %b) {
define i1 @f8(i32 %a, i32 %b) {
; CHECK-LABEL: f8:
-; CHECK: sub r0, r0, r1, asr #7
-; CHECK: clz r0, r0
-; CHECK: lsr r0, r0, #5
-; CHECK-T2: sub.w r0, r0, r1, asr #7
-; CHECK-T2: clz r0, r0
-; CHECK-T2: lsrs r0, r0, #5
+; CHECK: @ %bb.0:
+; CHECK-NEXT: sub r0, r0, r1, asr #7
+; CHECK-NEXT: clz r0, r0
+; CHECK-NEXT: lsr r0, r0, #5
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: f8:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: sub.w r0, r0, r1, asr #7
+; CHECK-T2-NEXT: clz r0, r0
+; CHECK-T2-NEXT: lsrs r0, r0, #5
+; CHECK-T2-NEXT: bx lr
%tmp = ashr i32 %b, 7
%tmp1 = icmp eq i32 %a, %tmp
ret i1 %tmp1
@@ -64,11 +95,17 @@ define i1 @f8(i32 %a, i32 %b) {
define i1 @f9(i32 %a) {
; CHECK-LABEL: f9:
-; CHECK: subs r0, r0, r0, ror #8
-; CHECK: movwne r0, #1
-; CHECK-T2: subs.w r0, r0, r0, ror #8
-; CHECK-T2: it ne
-; CHECK-T2: movne r0, #1
+; CHECK: @ %bb.0:
+; CHECK-NEXT: subs r0, r0, r0, ror #8
+; CHECK-NEXT: movwne r0, #1
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: f9:
+; CHECK-T2: @ %bb.0:
+; CHECK-T2-NEXT: subs.w r0, r0, r0, ror #8
+; CHECK-T2-NEXT: it ne
+; CHECK-T2-NEXT: movne r0, #1
+; CHECK-T2-NEXT: bx lr
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
%tmp = or i32 %l8, %r8
@@ -76,14 +113,23 @@ define i1 @f9(i32 %a) {
ret i1 %tmp1
}
-; CHECK-LABEL: swap_cmp_shl
-; CHECK: mov r2, #0
-; CHECK: cmp r1, r0, lsl #11
-; CHECK: movwlt r2, #1
-; CHECK-T2: mov{{.*}} r2, #0
-; CHECK-T2: cmp.w r1, r0, lsl #11
-; CHECK-T2: movlt r2, #1
define arm_aapcscc i32 @swap_cmp_shl(i32 %a, i32 %b) {
+; CHECK-LABEL: swap_cmp_shl:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: cmp r1, r0, lsl #11
+; CHECK-NEXT: movwlt r2, #1
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: swap_cmp_shl:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r2, #0
+; CHECK-T2-NEXT: cmp.w r1, r0, lsl #11
+; CHECK-T2-NEXT: it lt
+; CHECK-T2-NEXT: movlt r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
entry:
%shift = shl i32 %a, 11
%cmp = icmp sgt i32 %shift, %b
@@ -91,14 +137,23 @@ entry:
ret i32 %conv
}
-; CHECK-LABEL: swap_cmp_lshr
-; CHECK: mov r2, #0
-; CHECK: cmp r1, r0, lsr #11
-; CHECK: movwhi r2, #1
-; CHECK-T2: mov{{.*}} r2, #0
-; CHECK-T2: cmp.w r1, r0, lsr #11
-; CHECK-T2: movhi r2, #1
define arm_aapcscc i32 @swap_cmp_lshr(i32 %a, i32 %b) {
+; CHECK-LABEL: swap_cmp_lshr:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: cmp r1, r0, lsr #11
+; CHECK-NEXT: movwhi r2, #1
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: swap_cmp_lshr:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r2, #0
+; CHECK-T2-NEXT: cmp.w r1, r0, lsr #11
+; CHECK-T2-NEXT: it hi
+; CHECK-T2-NEXT: movhi r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
entry:
%shift = lshr i32 %a, 11
%cmp = icmp ult i32 %shift, %b
@@ -106,14 +161,23 @@ entry:
ret i32 %conv
}
-; CHECK-LABEL: swap_cmp_ashr
-; CHECK: mov r2, #0
-; CHECK: cmp r1, r0, asr #11
-; CHECK: movwle r2, #1
-; CHECK-T2: mov{{.*}} r2, #0
-; CHECK-T2: cmp.w r1, r0, asr #11
-; CHECK-T2: movle r2, #1
define arm_aapcscc i32 @swap_cmp_ashr(i32 %a, i32 %b) {
+; CHECK-LABEL: swap_cmp_ashr:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: cmp r1, r0, asr #11
+; CHECK-NEXT: movwle r2, #1
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: swap_cmp_ashr:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r2, #0
+; CHECK-T2-NEXT: cmp.w r1, r0, asr #11
+; CHECK-T2-NEXT: it le
+; CHECK-T2-NEXT: movle r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
entry:
%shift = ashr i32 %a, 11
%cmp = icmp sge i32 %shift, %b
@@ -121,14 +185,23 @@ entry:
ret i32 %conv
}
-; CHECK-LABEL: swap_cmp_rotr
-; CHECK: mov r2, #0
-; CHECK: cmp r1, r0, ror #11
-; CHECK: movwls r2, #1
-; CHECK-T2: mov{{.*}} r2, #0
-; CHECK-T2: cmp.w r1, r0, ror #11
-; CHECK-T2: movls r2, #1
define arm_aapcscc i32 @swap_cmp_rotr(i32 %a, i32 %b) {
+; CHECK-LABEL: swap_cmp_rotr:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: cmp r1, r0, ror #11
+; CHECK-NEXT: movwls r2, #1
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
+;
+; CHECK-T2-LABEL: swap_cmp_rotr:
+; CHECK-T2: @ %bb.0: @ %entry
+; CHECK-T2-NEXT: movs r2, #0
+; CHECK-T2-NEXT: cmp.w r1, r0, ror #11
+; CHECK-T2-NEXT: it ls
+; CHECK-T2-NEXT: movls r2, #1
+; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: bx lr
entry:
%lsr = lshr i32 %a, 11
%lsl = shl i32 %a, 21
diff --git a/llvm/test/CodeGen/Thumb2/float-cmp.ll b/llvm/test/CodeGen/Thumb2/float-cmp.ll
index ed80544377204..03a176cde278c 100644
--- a/llvm/test/CodeGen/Thumb2/float-cmp.ll
+++ b/llvm/test/CodeGen/Thumb2/float-cmp.ll
@@ -1,303 +1,766 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP
-
-
define i1 @cmp_f_false(float %a, float %b) {
; CHECK-LABEL: cmp_f_false:
-; NONE: movs r0, #0
-; HARD: movs r0, #0
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: bx lr
%1 = fcmp false float %a, %b
ret i1 %1
}
+
define i1 @cmp_f_oeq(float %a, float %b) {
-; CHECK-LABEL: cmp_f_oeq:
-; NONE: bl __aeabi_fcmpeq
-; HARD: vcmp.f32
-; HARD: moveq r0, #1
+; NONE-LABEL: cmp_f_oeq:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmpeq
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_oeq:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it eq
+; SP-NEXT: moveq r0, #1
+; SP-NEXT: bx lr
%1 = fcmp oeq float %a, %b
ret i1 %1
}
+
define i1 @cmp_f_ogt(float %a, float %b) {
-; CHECK-LABEL: cmp_f_ogt:
-; NONE: bl __aeabi_fcmpgt
-; HARD: vcmp.f32
-; HARD: movgt r0, #1
+; NONE-LABEL: cmp_f_ogt:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmpgt
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_ogt:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it gt
+; SP-NEXT: movgt r0, #1
+; SP-NEXT: bx lr
%1 = fcmp ogt float %a, %b
ret i1 %1
}
+
define i1 @cmp_f_oge(float %a, float %b) {
-; CHECK-LABEL: cmp_f_oge:
-; NONE: bl __aeabi_fcmpge
-; HARD: vcmp.f32
-; HARD: movge r0, #1
+; NONE-LABEL: cmp_f_oge:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmpge
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_oge:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it ge
+; SP-NEXT: movge r0, #1
+; SP-NEXT: bx lr
%1 = fcmp oge float %a, %b
ret i1 %1
}
+
define i1 @cmp_f_olt(float %a, float %b) {
-; CHECK-LABEL: cmp_f_olt:
-; NONE: bl __aeabi_fcmplt
-; HARD: vcmp.f32
-; HARD: movmi r0, #1
+; NONE-LABEL: cmp_f_olt:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmplt
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_olt:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it mi
+; SP-NEXT: movmi r0, #1
+; SP-NEXT: bx lr
%1 = fcmp olt float %a, %b
ret i1 %1
}
define i1 @cmp_f_ole(float %a, float %b) {
-; CHECK-LABEL: cmp_f_ole:
-; NONE: bl __aeabi_fcmple
-; HARD: vcmp.f32
-; HARD: movls r0, #1
+; NONE-LABEL: cmp_f_ole:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmple
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_ole:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it ls
+; SP-NEXT: movls r0, #1
+; SP-NEXT: bx lr
%1 = fcmp ole float %a, %b
ret i1 %1
}
+
define i1 @cmp_f_one(float %a, float %b) {
-; CHECK-LABEL: cmp_f_one:
-; NONE: bl __aeabi_fcmpeq
-; NONE: bl __aeabi_fcmpun
-; HARD: vcmp.f32
-; HARD: movmi r0, #1
-; HARD: movgt r0, #1
+; NONE-LABEL: cmp_f_one:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r4, r5, r6, lr}
+; NONE-NEXT: push {r4, r5, r6, lr}
+; NONE-NEXT: mov r4, r1
+; NONE-NEXT: mov r5, r0
+; NONE-NEXT: bl __aeabi_fcmpeq
+; NONE-NEXT: mov r6, r0
+; NONE-NEXT: mov r0, r5
+; NONE-NEXT: mov r1, r4
+; NONE-NEXT: bl __aeabi_fcmpun
+; NONE-NEXT: orrs r0, r6
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r4, r5, r6, pc}
+;
+; SP-LABEL: cmp_f_one:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it mi
+; SP-NEXT: movmi r0, #1
+; SP-NEXT: it gt
+; SP-NEXT: movgt r0, #1
+; SP-NEXT: bx lr
%1 = fcmp one float %a, %b
ret i1 %1
}
define i1 @cmp_f_ord(float %a, float %b) {
-; CHECK-LABEL: cmp_f_ord:
-; NONE: bl __aeabi_fcmpun
-; HARD: vcmp.f32
-; HARD: movvc r0, #1
+; NONE-LABEL: cmp_f_ord:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmpun
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_ord:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it vc
+; SP-NEXT: movvc r0, #1
+; SP-NEXT: bx lr
%1 = fcmp ord float %a, %b
ret i1 %1
}
+
define i1 @cmp_f_ueq(float %a, float %b) {
-; CHECK-LABEL: cmp_f_ueq:
-; NONE: bl __aeabi_fcmpeq
-; NONE: bl __aeabi_fcmpun
-; HARD: vcmp.f32
-; HARD: moveq r0, #1
-; HARD: movvs r0, #1
+; NONE-LABEL: cmp_f_ueq:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r4, r5, r6, lr}
+; NONE-NEXT: push {r4, r5, r6, lr}
+; NONE-NEXT: mov r4, r1
+; NONE-NEXT: mov r5, r0
+; NONE-NEXT: bl __aeabi_fcmpeq
+; NONE-NEXT: mov r6, r0
+; NONE-NEXT: mov r0, r5
+; NONE-NEXT: mov r1, r4
+; NONE-NEXT: bl __aeabi_fcmpun
+; NONE-NEXT: orrs r0, r6
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r4, r5, r6, pc}
+;
+; SP-LABEL: cmp_f_ueq:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it eq
+; SP-NEXT: moveq r0, #1
+; SP-NEXT: it vs
+; SP-NEXT: movvs r0, #1
+; SP-NEXT: bx lr
%1 = fcmp ueq float %a, %b
ret i1 %1
}
define i1 @cmp_f_ugt(float %a, float %b) {
-; CHECK-LABEL: cmp_f_ugt:
-; NONE: bl __aeabi_fcmple
-; NONE-NEXT: clz r0, r0
-; NONE-NEXT: lsrs r0, r0, #5
-; HARD: vcmp.f32
-; HARD: movhi r0, #1
+; NONE-LABEL: cmp_f_ugt:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmple
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_ugt:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it hi
+; SP-NEXT: movhi r0, #1
+; SP-NEXT: bx lr
%1 = fcmp ugt float %a, %b
ret i1 %1
}
define i1 @cmp_f_uge(float %a, float %b) {
-; CHECK-LABEL: cmp_f_uge:
-; NONE: bl __aeabi_fcmplt
-; NONE-NEXT: clz r0, r0
-; NONE-NEXT: lsrs r0, r0, #5
-; HARD: vcmp.f32
-; HARD: movpl r0, #1
+; NONE-LABEL: cmp_f_uge:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmplt
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_uge:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it pl
+; SP-NEXT: movpl r0, #1
+; SP-NEXT: bx lr
%1 = fcmp uge float %a, %b
ret i1 %1
}
+
define i1 @cmp_f_ult(float %a, float %b) {
-; CHECK-LABEL: cmp_f_ult:
-; NONE: bl __aeabi_fcmpge
-; NONE-NEXT: clz r0, r0
-; NONE-NEXT: lsrs r0, r0, #5
-; HARD: vcmp.f32
-; HARD: movlt r0, #1
+; NONE-LABEL: cmp_f_ult:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmpge
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_ult:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it lt
+; SP-NEXT: movlt r0, #1
+; SP-NEXT: bx lr
%1 = fcmp ult float %a, %b
ret i1 %1
}
define i1 @cmp_f_ule(float %a, float %b) {
-; CHECK-LABEL: cmp_f_ule:
-; NONE: bl __aeabi_fcmpgt
-; NONE-NEXT: clz r0, r0
-; NONE-NEXT: lsrs r0, r0, #5
-; HARD: vcmp.f32
-; HARD: movle r0, #1
+; NONE-LABEL: cmp_f_ule:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmpgt
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_ule:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it le
+; SP-NEXT: movle r0, #1
+; SP-NEXT: bx lr
%1 = fcmp ule float %a, %b
ret i1 %1
}
+
define i1 @cmp_f_une(float %a, float %b) {
-; CHECK-LABEL: cmp_f_une:
-; NONE: bl __aeabi_fcmpeq
-; HARD: vcmp.f32
-; HARD: movne r0, #1
+; NONE-LABEL: cmp_f_une:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmpeq
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_une:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: bx lr
%1 = fcmp une float %a, %b
ret i1 %1
}
+
define i1 @cmp_f_uno(float %a, float %b) {
-; CHECK-LABEL: cmp_f_uno:
-; NONE: bl __aeabi_fcmpun
-; HARD: vcmp.f32
-; HARD: movvs r0, #1
+; NONE-LABEL: cmp_f_uno:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_fcmpun
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_f_uno:
+; SP: @ %bb.0:
+; SP-NEXT: vcmp.f32 s0, s1
+; SP-NEXT: movs r0, #0
+; SP-NEXT: vmrs APSR_nzcv, fpscr
+; SP-NEXT: it vs
+; SP-NEXT: movvs r0, #1
+; SP-NEXT: bx lr
%1 = fcmp uno float %a, %b
ret i1 %1
}
define i1 @cmp_f_true(float %a, float %b) {
; CHECK-LABEL: cmp_f_true:
-; NONE: movs r0, #1
-; HARD: movs r0, #1
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r0, #1
+; CHECK-NEXT: bx lr
%1 = fcmp true float %a, %b
ret i1 %1
}
define i1 @cmp_d_false(double %a, double %b) {
; CHECK-LABEL: cmp_d_false:
-; NONE: movs r0, #0
-; HARD: movs r0, #0
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: bx lr
%1 = fcmp false double %a, %b
ret i1 %1
}
define i1 @cmp_d_oeq(double %a, double %b) {
-; CHECK-LABEL: cmp_d_oeq:
-; NONE: bl __aeabi_dcmpeq
-; SP: bl __aeabi_dcmpeq
-; DP: vcmp.f64
-; DP: moveq r0, #1
+; NONE-LABEL: cmp_d_oeq:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmpeq
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_oeq:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmpeq
+; SP-NEXT: cmp r0, #0
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: pop {r7, pc}
%1 = fcmp oeq double %a, %b
ret i1 %1
}
define i1 @cmp_d_ogt(double %a, double %b) {
-; CHECK-LABEL: cmp_d_ogt:
-; NONE: bl __aeabi_dcmpgt
-; SP: bl __aeabi_dcmpgt
-; DP: vcmp.f64
-; DP: movgt r0, #1
+; NONE-LABEL: cmp_d_ogt:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmpgt
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_ogt:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmpgt
+; SP-NEXT: cmp r0, #0
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: pop {r7, pc}
%1 = fcmp ogt double %a, %b
ret i1 %1
}
+
define i1 @cmp_d_oge(double %a, double %b) {
-; CHECK-LABEL: cmp_d_oge:
-; NONE: bl __aeabi_dcmpge
-; SP: bl __aeabi_dcmpge
-; DP: vcmp.f64
-; DP: movge r0, #1
+; NONE-LABEL: cmp_d_oge:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmpge
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_oge:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmpge
+; SP-NEXT: cmp r0, #0
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: pop {r7, pc}
%1 = fcmp oge double %a, %b
ret i1 %1
}
define i1 @cmp_d_olt(double %a, double %b) {
-; CHECK-LABEL: cmp_d_olt:
-; NONE: bl __aeabi_dcmplt
-; SP: bl __aeabi_dcmplt
-; DP: vcmp.f64
-; DP: movmi r0, #1
+; NONE-LABEL: cmp_d_olt:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmplt
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_olt:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmplt
+; SP-NEXT: cmp r0, #0
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: pop {r7, pc}
%1 = fcmp olt double %a, %b
ret i1 %1
}
+
define i1 @cmp_d_ole(double %a, double %b) {
-; CHECK-LABEL: cmp_d_ole:
-; NONE: bl __aeabi_dcmple
-; SP: bl __aeabi_dcmple
-; DP: vcmp.f64
-; DP: movls r0, #1
+; NONE-LABEL: cmp_d_ole:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmple
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_ole:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmple
+; SP-NEXT: cmp r0, #0
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: pop {r7, pc}
%1 = fcmp ole double %a, %b
ret i1 %1
}
+
define i1 @cmp_d_one(double %a, double %b) {
-; CHECK-LABEL: cmp_d_one:
-; NONE: bl __aeabi_dcmpeq
-; NONE: bl __aeabi_dcmpun
-; SP: bl __aeabi_dcmpun
-; SP: eor r8, r0, #1
-; SP: bl __aeabi_dcmpeq
-; SP-NEXT: clz r0, r0
-; SP-NEXT: lsrs r0, r0, #5
-; SP-NEXT: ands.w r0, r0, r8
+; NONE-LABEL: cmp_d_one:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; NONE-NEXT: push.w {r4, r5, r6, r7, r8, lr}
+; NONE-NEXT: mov r4, r3
+; NONE-NEXT: mov r5, r2
+; NONE-NEXT: mov r6, r1
+; NONE-NEXT: mov r7, r0
+; NONE-NEXT: bl __aeabi_dcmpeq
+; NONE-NEXT: mov r8, r0
+; NONE-NEXT: mov r0, r7
+; NONE-NEXT: mov r1, r6
+; NONE-NEXT: mov r2, r5
+; NONE-NEXT: mov r3, r4
+; NONE-NEXT: bl __aeabi_dcmpun
+; NONE-NEXT: orr.w r0, r0, r8
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
+;
+; SP-LABEL: cmp_d_one:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; SP-NEXT: push.w {r4, r5, r6, r7, r8, lr}
+; SP-NEXT: vmov r4, r5, d0
+; SP-NEXT: vmov r6, r7, d1
+; SP-NEXT: mov r0, r4
+; SP-NEXT: mov r1, r5
+; SP-NEXT: mov r2, r6
+; SP-NEXT: mov r3, r7
+; SP-NEXT: bl __aeabi_dcmpun
+; SP-NEXT: eor r8, r0, #1
+; SP-NEXT: mov r0, r4
+; SP-NEXT: mov r1, r5
+; SP-NEXT: mov r2, r6
+; SP-NEXT: mov r3, r7
+; SP-NEXT: bl __aeabi_dcmpeq
+; SP-NEXT: clz r0, r0
+; SP-NEXT: lsrs r0, r0, #5
+; SP-NEXT: ands.w r0, r0, r8
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
-; DP: vcmp.f64
-; DP: movmi r0, #1
-; DP: movgt r0, #1
%1 = fcmp one double %a, %b
ret i1 %1
}
+
define i1 @cmp_d_ord(double %a, double %b) {
-; CHECK-LABEL: cmp_d_ord:
-; NONE: bl __aeabi_dcmpun
-; SP: bl __aeabi_dcmpun
-; DP: vcmp.f64
-; DP: movvc r0, #1
+; NONE-LABEL: cmp_d_ord:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmpun
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_ord:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmpun
+; SP-NEXT: clz r0, r0
+; SP-NEXT: lsrs r0, r0, #5
+; SP-NEXT: pop {r7, pc}
%1 = fcmp ord double %a, %b
ret i1 %1
}
+
define i1 @cmp_d_ugt(double %a, double %b) {
-; CHECK-LABEL: cmp_d_ugt:
-; NONE: bl __aeabi_dcmple
-; SP: bl __aeabi_dcmple
-; DP: vcmp.f64
-; DP: movhi r0, #1
+; NONE-LABEL: cmp_d_ugt:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmple
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_ugt:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmple
+; SP-NEXT: clz r0, r0
+; SP-NEXT: lsrs r0, r0, #5
+; SP-NEXT: pop {r7, pc}
%1 = fcmp ugt double %a, %b
ret i1 %1
}
define i1 @cmp_d_ult(double %a, double %b) {
-; CHECK-LABEL: cmp_d_ult:
-; NONE: bl __aeabi_dcmpge
-; SP: bl __aeabi_dcmpge
-; DP: vcmp.f64
-; DP: movlt r0, #1
+; NONE-LABEL: cmp_d_ult:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmpge
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_ult:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmpge
+; SP-NEXT: clz r0, r0
+; SP-NEXT: lsrs r0, r0, #5
+; SP-NEXT: pop {r7, pc}
%1 = fcmp ult double %a, %b
ret i1 %1
}
-
define i1 @cmp_d_uno(double %a, double %b) {
-; CHECK-LABEL: cmp_d_uno:
-; NONE: bl __aeabi_dcmpun
-; SP: bl __aeabi_dcmpun
-; DP: vcmp.f64
-; DP: movvs r0, #1
+; NONE-LABEL: cmp_d_uno:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmpun
+; NONE-NEXT: cmp r0, #0
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_uno:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmpun
+; SP-NEXT: cmp r0, #0
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: pop {r7, pc}
%1 = fcmp uno double %a, %b
ret i1 %1
}
define i1 @cmp_d_true(double %a, double %b) {
; CHECK-LABEL: cmp_d_true:
-; NONE: movs r0, #1
-; HARD: movs r0, #1
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r0, #1
+; CHECK-NEXT: bx lr
%1 = fcmp true double %a, %b
ret i1 %1
}
define i1 @cmp_d_ueq(double %a, double %b) {
-; CHECK-LABEL: cmp_d_ueq:
-; NONE: bl __aeabi_dcmpeq
-; NONE: bl __aeabi_dcmpun
-; SP: bl __aeabi_dcmpeq
-; SP: bl __aeabi_dcmpun
-; DP: vcmp.f64
-; DP: moveq r0, #1
-; DP: movvs r0, #1
+; NONE-LABEL: cmp_d_ueq:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; NONE-NEXT: push.w {r4, r5, r6, r7, r8, lr}
+; NONE-NEXT: mov r4, r3
+; NONE-NEXT: mov r5, r2
+; NONE-NEXT: mov r6, r1
+; NONE-NEXT: mov r7, r0
+; NONE-NEXT: bl __aeabi_dcmpeq
+; NONE-NEXT: mov r8, r0
+; NONE-NEXT: mov r0, r7
+; NONE-NEXT: mov r1, r6
+; NONE-NEXT: mov r2, r5
+; NONE-NEXT: mov r3, r4
+; NONE-NEXT: bl __aeabi_dcmpun
+; NONE-NEXT: orrs.w r0, r0, r8
+; NONE-NEXT: it ne
+; NONE-NEXT: movne r0, #1
+; NONE-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
+;
+; SP-LABEL: cmp_d_ueq:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; SP-NEXT: push.w {r4, r5, r6, r7, r8, lr}
+; SP-NEXT: vmov r4, r5, d0
+; SP-NEXT: vmov r6, r8, d1
+; SP-NEXT: mov r0, r4
+; SP-NEXT: mov r1, r5
+; SP-NEXT: mov r2, r6
+; SP-NEXT: mov r3, r8
+; SP-NEXT: bl __aeabi_dcmpeq
+; SP-NEXT: mov r7, r0
+; SP-NEXT: cmp r0, #0
+; SP-NEXT: mov r0, r4
+; SP-NEXT: mov r1, r5
+; SP-NEXT: mov r2, r6
+; SP-NEXT: mov r3, r8
+; SP-NEXT: it ne
+; SP-NEXT: movne r7, #1
+; SP-NEXT: bl __aeabi_dcmpun
+; SP-NEXT: cmp r0, #0
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: orrs r0, r7
+; SP-NEXT: it ne
+; SP-NEXT: movne r0, #1
+; SP-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
%1 = fcmp ueq double %a, %b
ret i1 %1
}
define i1 @cmp_d_uge(double %a, double %b) {
-; CHECK-LABEL: cmp_d_uge:
-; NONE: bl __aeabi_dcmplt
-; SP: bl __aeabi_dcmplt
-; DP: vcmp.f64
-; DP: movpl r0, #1
+; NONE-LABEL: cmp_d_uge:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmplt
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_uge:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmplt
+; SP-NEXT: clz r0, r0
+; SP-NEXT: lsrs r0, r0, #5
+; SP-NEXT: pop {r7, pc}
%1 = fcmp uge double %a, %b
ret i1 %1
}
define i1 @cmp_d_ule(double %a, double %b) {
-; CHECK-LABEL: cmp_d_ule:
-; NONE: bl __aeabi_dcmpgt
-; SP: bl __aeabi_dcmpgt
-; DP: vcmp.f64
-; DP: movle r0, #1
+; NONE-LABEL: cmp_d_ule:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmpgt
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_ule:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmpgt
+; SP-NEXT: clz r0, r0
+; SP-NEXT: lsrs r0, r0, #5
+; SP-NEXT: pop {r7, pc}
%1 = fcmp ule double %a, %b
ret i1 %1
}
define i1 @cmp_d_une(double %a, double %b) {
-; CHECK-LABEL: cmp_d_une:
-; NONE: bl __aeabi_dcmpeq
-; SP: bl __aeabi_dcmpeq
-; DP: vcmp.f64
-; DP: movne r0, #1
+; NONE-LABEL: cmp_d_une:
+; NONE: @ %bb.0:
+; NONE-NEXT: .save {r7, lr}
+; NONE-NEXT: push {r7, lr}
+; NONE-NEXT: bl __aeabi_dcmpeq
+; NONE-NEXT: clz r0, r0
+; NONE-NEXT: lsrs r0, r0, #5
+; NONE-NEXT: pop {r7, pc}
+;
+; SP-LABEL: cmp_d_une:
+; SP: @ %bb.0:
+; SP-NEXT: .save {r7, lr}
+; SP-NEXT: push {r7, lr}
+; SP-NEXT: vmov r0, r1, d0
+; SP-NEXT: vmov r2, r3, d1
+; SP-NEXT: bl __aeabi_dcmpeq
+; SP-NEXT: clz r0, r0
+; SP-NEXT: lsrs r0, r0, #5
+; SP-NEXT: pop {r7, pc}
%1 = fcmp une double %a, %b
ret i1 %1
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; DP: {{.*}}
+; HARD: {{.*}}
>From a2c67ae48992cb91836cc1c532b5d3aeb217877b Mon Sep 17 00:00:00 2001
From: Mike-Goutokuji <gfunni234 at gmail.com>
Date: Wed, 27 May 2026 20:32:56 -0400
Subject: [PATCH 2/2] [ARM] Lower SetCC like we do on AArch64
Lower floats and integers in SetCC and bring the transformations that only exist in SelectCC because they are not folded in SetCC.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 87 ++++++-----
llvm/lib/Target/ARM/ARMISelLowering.h | 2 +-
llvm/test/Analysis/CostModel/ARM/abs.ll | 4 +-
.../CostModel/ARM/active_lane_mask.ll | 8 +-
.../Analysis/CostModel/ARM/arith-overflow.ll | 36 ++---
.../test/Analysis/CostModel/ARM/arith-ssat.ll | 36 ++---
.../test/Analysis/CostModel/ARM/arith-usat.ll | 24 +--
llvm/test/Analysis/CostModel/ARM/cmps.ll | 16 +-
llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll | 16 +-
llvm/test/Analysis/CostModel/ARM/mve-abs.ll | 6 +-
llvm/test/Analysis/CostModel/ARM/mve-cmp.ll | 10 +-
.../test/Analysis/CostModel/ARM/mve-minmax.ll | 32 ++--
.../test/Analysis/CostModel/ARM/reduce-and.ll | 12 +-
llvm/test/Analysis/CostModel/ARM/reduce-or.ll | 12 +-
.../Analysis/CostModel/ARM/reduce-smax.ll | 16 +-
.../Analysis/CostModel/ARM/reduce-smin.ll | 16 +-
.../Analysis/CostModel/ARM/reduce-umax.ll | 16 +-
.../Analysis/CostModel/ARM/reduce-umin.ll | 16 +-
llvm/test/CodeGen/ARM/cmp.ll | 18 +--
llvm/test/CodeGen/ARM/umulo-32.ll | 7 +-
llvm/test/CodeGen/Thumb/smul_fix_sat.ll | 2 +-
llvm/test/CodeGen/Thumb2/float-cmp.ll | 6 +-
llvm/test/CodeGen/Thumb2/mve-no-fp.ll | 63 +++-----
.../LoopUnroll/ARM/unroll-optsize.ll | 28 ++--
.../LoopVectorize/ARM/optsize_minsize.ll | 141 ++++++++++++++++--
25 files changed, 369 insertions(+), 261 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 35c46c3f0a75a..4660fbcf5be9c 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1201,9 +1201,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
- setOperationAction(ISD::SETCC, MVT::i32, Expand);
- setOperationAction(ISD::SETCC, MVT::f32, Expand);
- setOperationAction(ISD::SETCC, MVT::f64, Expand);
+ setOperationAction(ISD::SETCC, MVT::i32, Custom);
+ setOperationAction(ISD::SETCC, MVT::f32, Custom);
+ setOperationAction(ISD::SETCC, MVT::f64, Custom);
setOperationAction(ISD::SELECT, MVT::i32, Custom);
setOperationAction(ISD::SELECT, MVT::f32, Custom);
setOperationAction(ISD::SELECT, MVT::f64, Custom);
@@ -1211,7 +1211,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
if (Subtarget->hasFullFP16()) {
- setOperationAction(ISD::SETCC, MVT::f16, Expand);
+ setOperationAction(ISD::SETCC, MVT::f16, Custom);
setOperationAction(ISD::SELECT, MVT::f16, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
}
@@ -4974,8 +4974,7 @@ SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
}
}
- return DAG.getSelectCC(dl, Cond,
- DAG.getConstant(0, dl, Cond.getValueType()),
+ return DAG.getSelectCC(dl, Cond, DAG.getConstant(0, dl, Cond.getValueType()),
SelectTrue, SelectFalse, ISD::SETNE);
}
@@ -5306,12 +5305,6 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ISD::AND, dl, VT, LHS, Shift);
}
-
- // (SELECT_CC setlt, x, 0, 1, 0) -> SRL(x, bw-1)
- if (CC == ISD::SETLT && isNullConstant(RHS) && isOneConstant(TrueVal) &&
- isNullConstant(FalseVal) && LHS.getValueType() == VT)
- return DAG.getNode(ISD::SRL, dl, VT, LHS,
- DAG.getConstant(VT.getSizeInBits() - 1, dl, VT));
}
if (LHS.getValueType() == MVT::i32) {
@@ -10323,42 +10316,65 @@ static void ReplaceCMP_SWAP_64Results(SDNode *N,
Results.push_back(SDValue(CmpSwap, 2));
}
-SDValue ARMTargetLowering::LowerFSETCC(SDValue Op, SelectionDAG &DAG) const {
+SDValue ARMTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
+
+ if (Op.getValueType().isVector())
+ return LowerVSETCC(Op, DAG, Subtarget);
+
+ bool IsStrict = Op->isStrictFPOpcode();
+ bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS;
+ unsigned OpNo = IsStrict ? 1 : 0;
+ SDValue Chain;
+ if (IsStrict)
+ Chain = Op.getOperand(0);
+ SDValue LHS = Op.getOperand(OpNo + 0);
+ SDValue RHS = Op.getOperand(OpNo + 1);
+ ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(OpNo + 2))->get();
SDLoc dl(Op);
+
+ // We chose ZeroOrOneBooleanContents, so use zero and one.
EVT VT = Op.getValueType();
- SDValue Chain = Op.getOperand(0);
- SDValue LHS = Op.getOperand(1);
- SDValue RHS = Op.getOperand(2);
- ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get();
- bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS;
+ SDValue TrueVal = DAG.getConstant(1, dl, VT);
+ SDValue FalseVal = DAG.getConstant(0, dl, VT);
- // If we don't have instructions of this float type then soften to a libcall
- // and use SETCC instead.
if (isUnsupportedFloatingType(LHS.getValueType())) {
softenSetCCOperands(DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS,
Chain, IsSignaling);
+
+ // If softenSetCCOperands returned a scalar, use it.
if (!RHS.getNode()) {
- RHS = DAG.getConstant(0, dl, LHS.getValueType());
- CC = ISD::SETNE;
+ assert(LHS.getValueType() == Op.getValueType() &&
+ "Unexpected setcc expansion!");
+ return IsStrict ? DAG.getMergeValues({LHS, Chain}, dl) : LHS;
}
- SDValue Result = DAG.getNode(ISD::SETCC, dl, VT, LHS, RHS,
- DAG.getCondCode(CC));
- return DAG.getMergeValues({Result, Chain}, dl);
}
+ if (LHS.getValueType().isInteger()) {
+ // (SETCC setlt, x, 0) -> SRL(x, bw-1)
+ if (CC == ISD::SETLT && isNullConstant(RHS) && LHS.getValueType() == VT)
+ return DAG.getNode(ISD::SRL, dl, VT, LHS,
+ DAG.getConstant(VT.getSizeInBits() - 1, dl, VT));
+
+ SDValue ARMcc;
+ SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
+ SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, Cmp, DAG);
+ return IsStrict ? DAG.getMergeValues({Result, Chain}, dl) : Result;
+ }
+
+ // Now we know we're dealing with FP values.
+ assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||
+ LHS.getValueType() == MVT::f64);
+
ARMCC::CondCodes CondCode, CondCode2;
FPCCToARMCC(CC, CondCode, CondCode2);
-
- SDValue True = DAG.getConstant(1, dl, VT);
- SDValue False = DAG.getConstant(0, dl, VT);
SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, IsSignaling);
- SDValue Result = getCMOV(dl, VT, False, True, ARMcc, Cmp, DAG);
+ SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, Cmp, DAG);
if (CondCode2 != ARMCC::AL) {
- ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
- Result = getCMOV(dl, VT, Result, True, ARMcc, Cmp, DAG);
+ SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
+ Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, Cmp, DAG);
}
- return DAG.getMergeValues({Result, Chain}, dl);
+ return IsStrict ? DAG.getMergeValues({Result, Chain}, dl) : Result;
}
SDValue ARMTargetLowering::LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const {
@@ -10545,7 +10561,10 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::CTTZ:
case ISD::CTTZ_ZERO_POISON: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
- case ISD::SETCC: return LowerVSETCC(Op, DAG, Subtarget);
+ case ISD::STRICT_FSETCC:
+ case ISD::STRICT_FSETCCS:
+ case ISD::SETCC:
+ return LowerSETCC(Op, DAG);
case ISD::SETCCCARRY: return LowerSETCCCARRY(Op, DAG);
case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
@@ -10639,8 +10658,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
case ISD::STRICT_FP_EXTEND:
case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
- case ISD::STRICT_FSETCC:
- case ISD::STRICT_FSETCCS: return LowerFSETCC(Op, DAG);
case ISD::SPONENTRY:
return LowerSPONENTRY(Op, DAG);
case ISD::FP_TO_BF16:
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 10f5442d7429b..ba65eaedf33ea 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -605,7 +605,7 @@ class VectorType;
SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const;
diff --git a/llvm/test/Analysis/CostModel/ARM/abs.ll b/llvm/test/Analysis/CostModel/ARM/abs.ll
index e23af083e4758..fc6d7a862944f 100644
--- a/llvm/test/Analysis/CostModel/ARM/abs.ll
+++ b/llvm/test/Analysis/CostModel/ARM/abs.ll
@@ -11,8 +11,8 @@ define void @abs() {
; CHECK-T1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I8 = call i8 @llvm.abs.i8(i8 undef, i1 false)
; CHECK-T1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I16 = call i16 @llvm.abs.i16(i16 undef, i1 false)
; CHECK-T1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I32 = call i32 @llvm.abs.i32(i32 undef, i1 false)
-; CHECK-T1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:6 Lat:5 SizeLat:5 for: %I64 = call i64 @llvm.abs.i64(i64 undef, i1 false)
-; CHECK-T1-NEXT: Cost Model: Found costs of RThru:9 CodeSize:10 Lat:9 SizeLat:9 for: %I128 = call i128 @llvm.abs.i128(i128 undef, i1 false)
+; CHECK-T1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:7 Lat:6 SizeLat:6 for: %I64 = call i64 @llvm.abs.i64(i64 undef, i1 false)
+; CHECK-T1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:13 Lat:12 SizeLat:12 for: %I128 = call i128 @llvm.abs.i128(i128 undef, i1 false)
; CHECK-T1-NEXT: Cost Model: Found costs of 1 for: ret void
;
; CHECK-T2-LABEL: 'abs'
diff --git a/llvm/test/Analysis/CostModel/ARM/active_lane_mask.ll b/llvm/test/Analysis/CostModel/ARM/active_lane_mask.ll
index 38c43a5253a57..332c06bceb72b 100644
--- a/llvm/test/Analysis/CostModel/ARM/active_lane_mask.ll
+++ b/llvm/test/Analysis/CostModel/ARM/active_lane_mask.ll
@@ -3,10 +3,10 @@
define void @get_lane_mask() {
; CHECK-LABEL: 'get_lane_mask'
-; CHECK-NEXT: Cost Model: Found costs of RThru:176 CodeSize:192 Lat:176 SizeLat:176 for: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef)
-; CHECK-NEXT: Cost Model: Found costs of RThru:88 CodeSize:96 Lat:88 SizeLat:88 for: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef)
-; CHECK-NEXT: Cost Model: Found costs of RThru:44 CodeSize:48 Lat:44 SizeLat:44 for: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef)
-; CHECK-NEXT: Cost Model: Found costs of RThru:22 CodeSize:24 Lat:22 SizeLat:22 for: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found costs of RThru:192 CodeSize:208 Lat:192 SizeLat:192 for: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found costs of RThru:96 CodeSize:104 Lat:96 SizeLat:96 for: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found costs of RThru:48 CodeSize:52 Lat:48 SizeLat:48 for: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:26 Lat:24 SizeLat:24 for: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef)
; CHECK-NEXT: Cost Model: Found costs of RThru:96 CodeSize:112 Lat:96 SizeLat:96 for: %mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef)
; CHECK-NEXT: Cost Model: Found costs of RThru:48 CodeSize:56 Lat:48 SizeLat:48 for: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef)
; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:28 Lat:24 SizeLat:24 for: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll b/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
index 219b01dfc2dce..2c074943530ae 100644
--- a/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
+++ b/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
@@ -66,9 +66,9 @@ define i32 @sadd(i32 %arg) {
;
; MVE-LABEL: 'sadd'
; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:126 CodeSize:92 Lat:126 SizeLat:126 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.sadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:218 CodeSize:145 Lat:218 SizeLat:218 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.sadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:434 CodeSize:289 Lat:434 SizeLat:434 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:134 CodeSize:96 Lat:134 SizeLat:134 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.sadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:234 CodeSize:153 Lat:234 SizeLat:234 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.sadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:466 CodeSize:305 Lat:466 SizeLat:466 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:78 CodeSize:71 Lat:78 SizeLat:78 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.sadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef)
@@ -167,9 +167,9 @@ define i32 @uadd(i32 %arg) {
;
; MVE-LABEL: 'uadd'
; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:72 CodeSize:54 Lat:72 SizeLat:72 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.uadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:144 CodeSize:108 Lat:144 SizeLat:144 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.uadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:288 CodeSize:216 Lat:288 SizeLat:288 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.uadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:76 CodeSize:56 Lat:76 SizeLat:76 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.uadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:152 CodeSize:112 Lat:152 SizeLat:152 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.uadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:304 CodeSize:224 Lat:304 SizeLat:304 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.uadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.uadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:36 Lat:40 SizeLat:40 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.uadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef)
@@ -268,9 +268,9 @@ define i32 @ssub(i32 %arg) {
;
; MVE-LABEL: 'ssub'
; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:126 CodeSize:92 Lat:126 SizeLat:126 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.ssub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:218 CodeSize:145 Lat:218 SizeLat:218 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.ssub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:434 CodeSize:289 Lat:434 SizeLat:434 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.ssub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:134 CodeSize:96 Lat:134 SizeLat:134 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.ssub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:234 CodeSize:153 Lat:234 SizeLat:234 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.ssub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:466 CodeSize:305 Lat:466 SizeLat:466 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.ssub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:78 CodeSize:71 Lat:78 SizeLat:78 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.ssub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef)
@@ -369,9 +369,9 @@ define i32 @usub(i32 %arg) {
;
; MVE-LABEL: 'usub'
; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:72 CodeSize:54 Lat:72 SizeLat:72 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.usub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:144 CodeSize:108 Lat:144 SizeLat:144 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.usub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:288 CodeSize:216 Lat:288 SizeLat:288 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.usub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:76 CodeSize:56 Lat:76 SizeLat:76 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.usub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:152 CodeSize:112 Lat:152 SizeLat:152 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.usub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:304 CodeSize:224 Lat:304 SizeLat:304 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.usub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.usub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:36 Lat:40 SizeLat:40 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.usub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef)
@@ -470,9 +470,9 @@ define i32 @smul(i32 %arg) {
;
; MVE-LABEL: 'smul'
; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:912 CodeSize:74 Lat:108 SizeLat:108 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:1824 CodeSize:144 Lat:212 SizeLat:212 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:3648 CodeSize:284 Lat:420 SizeLat:420 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:916 CodeSize:76 Lat:112 SizeLat:112 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:1832 CodeSize:148 Lat:220 SizeLat:220 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:3664 CodeSize:292 Lat:436 SizeLat:436 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:284 CodeSize:150 Lat:152 SizeLat:152 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:872 CodeSize:328 Lat:332 SizeLat:332 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef)
@@ -571,9 +571,9 @@ define i32 @umul(i32 %arg) {
;
; MVE-LABEL: 'umul'
; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:876 CodeSize:38 Lat:72 SizeLat:72 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:1752 CodeSize:72 Lat:140 SizeLat:140 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:3504 CodeSize:140 Lat:276 SizeLat:276 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:880 CodeSize:40 Lat:76 SizeLat:76 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:1760 CodeSize:76 Lat:148 SizeLat:148 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:3520 CodeSize:148 Lat:292 SizeLat:292 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:186 CodeSize:149 Lat:150 SizeLat:150 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:484 CodeSize:326 Lat:328 SizeLat:328 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/arith-ssat.ll b/llvm/test/Analysis/CostModel/ARM/arith-ssat.ll
index 5d227a8359150..97873df5ca5b7 100644
--- a/llvm/test/Analysis/CostModel/ARM/arith-ssat.ll
+++ b/llvm/test/Analysis/CostModel/ARM/arith-ssat.ll
@@ -33,10 +33,10 @@ declare <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8>, <64 x i8>)
define i32 @add(i32 %arg) {
; V8M-LABEL: 'add'
-; V8M-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:30 CodeSize:34 Lat:30 SizeLat:30 for: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:60 CodeSize:68 Lat:60 SizeLat:60 for: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:120 CodeSize:136 Lat:120 SizeLat:120 for: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:10 SizeLat:10 for: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:32 CodeSize:36 Lat:32 SizeLat:32 for: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:64 CodeSize:72 Lat:64 SizeLat:64 for: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:128 CodeSize:144 Lat:128 SizeLat:128 for: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:5 SizeLat:5 for: %I32 = call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef)
; V8M-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:16 SizeLat:16 for: %V2I32 = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:32 CodeSize:40 Lat:32 SizeLat:32 for: %V4I32 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
@@ -58,7 +58,7 @@ define i32 @add(i32 %arg) {
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'add'
-; NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:7 Lat:7 SizeLat:7 for: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef)
+; NEON-NEXT: Cost Model: Found costs of RThru:10 CodeSize:9 Lat:9 SizeLat:9 for: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef)
; NEON-NEXT: Cost Model: Found costs of 1 for: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
; NEON-NEXT: Cost Model: Found costs of 4 for: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
; NEON-NEXT: Cost Model: Found costs of 8 for: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
@@ -83,10 +83,10 @@ define i32 @add(i32 %arg) {
; NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; MVE-LABEL: 'add'
-; MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:166 CodeSize:112 Lat:166 SizeLat:166 for: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:298 CodeSize:185 Lat:298 SizeLat:298 for: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:594 CodeSize:369 Lat:594 SizeLat:594 for: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:10 SizeLat:10 for: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:178 CodeSize:118 Lat:178 SizeLat:178 for: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:322 CodeSize:197 Lat:322 SizeLat:322 for: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:642 CodeSize:393 Lat:642 SizeLat:642 for: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of 1 for: %I32 = call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:100 CodeSize:70 Lat:100 SizeLat:100 for: %V2I32 = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
@@ -164,10 +164,10 @@ declare <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8>, <64 x i8>)
define i32 @sub(i32 %arg) {
; V8M-LABEL: 'sub'
-; V8M-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:30 CodeSize:34 Lat:30 SizeLat:30 for: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:60 CodeSize:68 Lat:60 SizeLat:60 for: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:120 CodeSize:136 Lat:120 SizeLat:120 for: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:10 SizeLat:10 for: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:32 CodeSize:36 Lat:32 SizeLat:32 for: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:64 CodeSize:72 Lat:64 SizeLat:64 for: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:128 CodeSize:144 Lat:128 SizeLat:128 for: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:5 SizeLat:5 for: %I32 = call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef)
; V8M-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:16 SizeLat:16 for: %V2I32 = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:32 CodeSize:40 Lat:32 SizeLat:32 for: %V4I32 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
@@ -189,7 +189,7 @@ define i32 @sub(i32 %arg) {
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'sub'
-; NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:7 Lat:7 SizeLat:7 for: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef)
+; NEON-NEXT: Cost Model: Found costs of RThru:10 CodeSize:9 Lat:9 SizeLat:9 for: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef)
; NEON-NEXT: Cost Model: Found costs of 1 for: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
; NEON-NEXT: Cost Model: Found costs of 4 for: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
; NEON-NEXT: Cost Model: Found costs of 8 for: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
@@ -214,10 +214,10 @@ define i32 @sub(i32 %arg) {
; NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; MVE-LABEL: 'sub'
-; MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:166 CodeSize:112 Lat:166 SizeLat:166 for: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:298 CodeSize:185 Lat:298 SizeLat:298 for: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:594 CodeSize:369 Lat:594 SizeLat:594 for: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:10 SizeLat:10 for: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:178 CodeSize:118 Lat:178 SizeLat:178 for: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:322 CodeSize:197 Lat:322 SizeLat:322 for: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:642 CodeSize:393 Lat:642 SizeLat:642 for: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of 1 for: %I32 = call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:100 CodeSize:70 Lat:100 SizeLat:100 for: %V2I32 = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/arith-usat.ll b/llvm/test/Analysis/CostModel/ARM/arith-usat.ll
index c843331c55e6e..d082747070d98 100644
--- a/llvm/test/Analysis/CostModel/ARM/arith-usat.ll
+++ b/llvm/test/Analysis/CostModel/ARM/arith-usat.ll
@@ -33,7 +33,7 @@ declare <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8>, <64 x i8>)
define i32 @add(i32 %arg) {
; V8M-LABEL: 'add'
-; V8M-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:10 SizeLat:10 for: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef)
; V8M-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:16 SizeLat:16 for: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:32 CodeSize:36 Lat:32 SizeLat:32 for: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:64 CodeSize:72 Lat:64 SizeLat:64 for: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
@@ -58,7 +58,7 @@ define i32 @add(i32 %arg) {
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'add'
-; NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:7 Lat:7 SizeLat:7 for: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef)
+; NEON-NEXT: Cost Model: Found costs of RThru:10 CodeSize:9 Lat:9 SizeLat:9 for: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef)
; NEON-NEXT: Cost Model: Found costs of 1 for: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
; NEON-NEXT: Cost Model: Found costs of 4 for: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
; NEON-NEXT: Cost Model: Found costs of 8 for: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
@@ -83,10 +83,10 @@ define i32 @add(i32 %arg) {
; NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; MVE-LABEL: 'add'
-; MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:74 CodeSize:55 Lat:74 SizeLat:74 for: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:148 CodeSize:110 Lat:148 SizeLat:148 for: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:296 CodeSize:220 Lat:296 SizeLat:296 for: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:10 SizeLat:10 for: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:78 CodeSize:57 Lat:78 SizeLat:78 for: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:156 CodeSize:114 Lat:156 SizeLat:156 for: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:312 CodeSize:228 Lat:312 SizeLat:312 for: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:5 SizeLat:5 for: %I32 = call i32 @llvm.uadd.sat.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:29 Lat:40 SizeLat:40 for: %V2I32 = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
@@ -164,7 +164,7 @@ declare <64 x i8> @llvm.usub.sat.v64i8(<64 x i8>, <64 x i8>)
define i32 @sub(i32 %arg) {
; V8M-LABEL: 'sub'
-; V8M-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:10 SizeLat:10 for: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef)
; V8M-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:16 SizeLat:16 for: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:32 CodeSize:36 Lat:32 SizeLat:32 for: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:64 CodeSize:72 Lat:64 SizeLat:64 for: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
@@ -189,7 +189,7 @@ define i32 @sub(i32 %arg) {
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'sub'
-; NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:7 Lat:7 SizeLat:7 for: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef)
+; NEON-NEXT: Cost Model: Found costs of RThru:10 CodeSize:9 Lat:9 SizeLat:9 for: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef)
; NEON-NEXT: Cost Model: Found costs of 1 for: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
; NEON-NEXT: Cost Model: Found costs of 4 for: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
; NEON-NEXT: Cost Model: Found costs of 8 for: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
@@ -214,10 +214,10 @@ define i32 @sub(i32 %arg) {
; NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; MVE-LABEL: 'sub'
-; MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:8 SizeLat:8 for: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:74 CodeSize:55 Lat:74 SizeLat:74 for: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:148 CodeSize:110 Lat:148 SizeLat:148 for: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:296 CodeSize:220 Lat:296 SizeLat:296 for: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:12 Lat:10 SizeLat:10 for: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:78 CodeSize:57 Lat:78 SizeLat:78 for: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:156 CodeSize:114 Lat:156 SizeLat:156 for: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:312 CodeSize:228 Lat:312 SizeLat:312 for: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:5 CodeSize:7 Lat:5 SizeLat:5 for: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:29 Lat:40 SizeLat:40 for: %V2I32 = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> undef, <2 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/cmps.ll b/llvm/test/Analysis/CostModel/ARM/cmps.ll
index 6b19be542a381..d9cf09fa7223a 100644
--- a/llvm/test/Analysis/CostModel/ARM/cmps.ll
+++ b/llvm/test/Analysis/CostModel/ARM/cmps.ll
@@ -11,7 +11,7 @@ define i32 @cmps() {
; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %a = icmp slt i8 undef, undef
; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %b = icmp ult i16 undef, undef
; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %c = icmp sge i32 undef, undef
-; CHECK-MVE-NEXT: Cost Model: Found costs of 1 for: %d = icmp ne i64 undef, undef
+; CHECK-MVE-NEXT: Cost Model: Found costs of 2 for: %d = icmp ne i64 undef, undef
; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %e = icmp slt <16 x i8> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %f = icmp ult <8 x i16> undef, undef
; CHECK-MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %g = icmp sge <4 x i32> undef, undef
@@ -29,16 +29,16 @@ define i32 @cmps() {
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %a = icmp slt i8 undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %b = icmp ult i16 undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %c = icmp sge i32 undef, undef
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %d = icmp ne i64 undef, undef
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 2 for: %d = icmp ne i64 undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 32 for: %e = icmp slt <16 x i8> undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 16 for: %f = icmp ult <8 x i16> undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 8 for: %g = icmp sge <4 x i32> undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %a7 = fcmp oge half undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %a8 = fcmp ogt float undef, undef
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %a9 = fcmp ogt double undef, undef
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 2 for: %a9 = fcmp ogt double undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 16 for: %a10 = fcmp olt <8 x half> undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 8 for: %a11 = fcmp oge <4 x float> undef, undef
-; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 6 for: %a12 = fcmp oge <2 x double> undef, undef
+; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 8 for: %a12 = fcmp oge <2 x double> undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: %p = icmp eq ptr undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 8 for: %q = icmp eq <4 x ptr> undef, undef
; CHECK-V8M-MAIN-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
@@ -47,16 +47,16 @@ define i32 @cmps() {
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %a = icmp slt i8 undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %b = icmp ult i16 undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %c = icmp sge i32 undef, undef
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %d = icmp ne i64 undef, undef
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 2 for: %d = icmp ne i64 undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 32 for: %e = icmp slt <16 x i8> undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 16 for: %f = icmp ult <8 x i16> undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 8 for: %g = icmp sge <4 x i32> undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %a7 = fcmp oge half undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %a8 = fcmp ogt float undef, undef
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %a9 = fcmp ogt double undef, undef
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 2 for: %a9 = fcmp ogt double undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 16 for: %a10 = fcmp olt <8 x half> undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 8 for: %a11 = fcmp oge <4 x float> undef, undef
-; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 6 for: %a12 = fcmp oge <2 x double> undef, undef
+; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 8 for: %a12 = fcmp oge <2 x double> undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: %p = icmp eq ptr undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 8 for: %q = icmp eq <4 x ptr> undef, undef
; CHECK-V8M-BASE-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
@@ -65,7 +65,7 @@ define i32 @cmps() {
; CHECK-V8R-NEXT: Cost Model: Found costs of 1 for: %a = icmp slt i8 undef, undef
; CHECK-V8R-NEXT: Cost Model: Found costs of 1 for: %b = icmp ult i16 undef, undef
; CHECK-V8R-NEXT: Cost Model: Found costs of 1 for: %c = icmp sge i32 undef, undef
-; CHECK-V8R-NEXT: Cost Model: Found costs of 1 for: %d = icmp ne i64 undef, undef
+; CHECK-V8R-NEXT: Cost Model: Found costs of 2 for: %d = icmp ne i64 undef, undef
; CHECK-V8R-NEXT: Cost Model: Found costs of 1 for: %e = icmp slt <16 x i8> undef, undef
; CHECK-V8R-NEXT: Cost Model: Found costs of 1 for: %f = icmp ult <8 x i16> undef, undef
; CHECK-V8R-NEXT: Cost Model: Found costs of 1 for: %g = icmp sge <4 x i32> undef, undef
diff --git a/llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll b/llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll
index af548f6216370..7268d61153ce8 100644
--- a/llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll
+++ b/llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll
@@ -117,16 +117,16 @@ define void @casts() {
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %f32u32 = call i32 @llvm.fptoui.sat.i32.f32(float undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:6 CodeSize:7 Lat:6 SizeLat:6 for: %f32s64 = call i64 @llvm.fptosi.sat.i64.f32(float undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 3 for: %f32u64 = call i64 @llvm.fptoui.sat.i64.f32(float undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:7 CodeSize:9 Lat:7 SizeLat:7 for: %f64s1 = call i1 @llvm.fptosi.sat.i1.f64(double undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:7 CodeSize:9 Lat:7 SizeLat:7 for: %f64u1 = call i1 @llvm.fptoui.sat.i1.f64(double undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:7 CodeSize:9 Lat:7 SizeLat:7 for: %f64s8 = call i8 @llvm.fptosi.sat.i8.f64(double undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:7 CodeSize:9 Lat:7 SizeLat:7 for: %f64u8 = call i8 @llvm.fptoui.sat.i8.f64(double undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:7 CodeSize:9 Lat:7 SizeLat:7 for: %f64s16 = call i16 @llvm.fptosi.sat.i16.f64(double undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:7 CodeSize:9 Lat:7 SizeLat:7 for: %f64u16 = call i16 @llvm.fptoui.sat.i16.f64(double undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:9 SizeLat:9 for: %f64s1 = call i1 @llvm.fptosi.sat.i1.f64(double undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:9 SizeLat:9 for: %f64u1 = call i1 @llvm.fptoui.sat.i1.f64(double undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:9 SizeLat:9 for: %f64s8 = call i8 @llvm.fptosi.sat.i8.f64(double undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:9 SizeLat:9 for: %f64u8 = call i8 @llvm.fptoui.sat.i8.f64(double undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:9 SizeLat:9 for: %f64s16 = call i16 @llvm.fptosi.sat.i16.f64(double undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:9 SizeLat:9 for: %f64u16 = call i16 @llvm.fptoui.sat.i16.f64(double undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %f64s32 = call i32 @llvm.fptosi.sat.i32.f64(double undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of 1 for: %f64u32 = call i32 @llvm.fptoui.sat.i32.f64(double undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:7 CodeSize:9 Lat:7 SizeLat:7 for: %f64s64 = call i64 @llvm.fptosi.sat.i64.f64(double undef)
-; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:7 CodeSize:9 Lat:7 SizeLat:7 for: %f64u64 = call i64 @llvm.fptoui.sat.i64.f64(double undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:9 SizeLat:9 for: %f64s64 = call i64 @llvm.fptosi.sat.i64.f64(double undef)
+; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:9 CodeSize:11 Lat:9 SizeLat:9 for: %f64u64 = call i64 @llvm.fptoui.sat.i64.f64(double undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:6 CodeSize:7 Lat:6 SizeLat:6 for: %v2f32s1 = call <2 x i1> @llvm.fptosi.sat.v2i1.v2f32(<2 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:6 CodeSize:7 Lat:6 SizeLat:6 for: %v2f32u1 = call <2 x i1> @llvm.fptoui.sat.v2i1.v2f32(<2 x float> undef)
; CHECK-MVEFP-NEXT: Cost Model: Found costs of RThru:6 CodeSize:7 Lat:6 SizeLat:6 for: %v2f32s8 = call <2 x i8> @llvm.fptosi.sat.v2i8.v2f32(<2 x float> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/mve-abs.ll b/llvm/test/Analysis/CostModel/ARM/mve-abs.ll
index 42563e8e34a94..409bc4cc9bbda 100644
--- a/llvm/test/Analysis/CostModel/ARM/mve-abs.ll
+++ b/llvm/test/Analysis/CostModel/ARM/mve-abs.ll
@@ -32,9 +32,9 @@ declare <64 x i8> @llvm.abs.v64i8(<64 x i8>, i1)
define i32 @abs(i32 %arg) {
; MVE-LABEL: 'abs'
; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call i64 @llvm.abs.i64(i64 undef, i1 false)
-; MVE-NEXT: Cost Model: Found costs of RThru:74 CodeSize:55 Lat:74 SizeLat:74 for: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> undef, i1 false)
-; MVE-NEXT: Cost Model: Found costs of RThru:148 CodeSize:110 Lat:148 SizeLat:148 for: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> undef, i1 false)
-; MVE-NEXT: Cost Model: Found costs of RThru:296 CodeSize:220 Lat:296 SizeLat:296 for: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> undef, i1 false)
+; MVE-NEXT: Cost Model: Found costs of RThru:78 CodeSize:57 Lat:78 SizeLat:78 for: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> undef, i1 false)
+; MVE-NEXT: Cost Model: Found costs of RThru:156 CodeSize:114 Lat:156 SizeLat:156 for: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> undef, i1 false)
+; MVE-NEXT: Cost Model: Found costs of RThru:312 CodeSize:228 Lat:312 SizeLat:312 for: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call i32 @llvm.abs.i32(i32 undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:29 Lat:40 SizeLat:40 for: %V2I32 = call <2 x i32> @llvm.abs.v2i32(<2 x i32> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> undef, i1 false)
diff --git a/llvm/test/Analysis/CostModel/ARM/mve-cmp.ll b/llvm/test/Analysis/CostModel/ARM/mve-cmp.ll
index 4e6ebbc593961..5cd822b4ec519 100644
--- a/llvm/test/Analysis/CostModel/ARM/mve-cmp.ll
+++ b/llvm/test/Analysis/CostModel/ARM/mve-cmp.ll
@@ -19,11 +19,11 @@ define void @icmp() {
; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v4i32 = icmp slt <4 x i32> undef, undef
; CHECK-NEXT: Cost Model: Found costs of RThru:36 CodeSize:34 Lat:36 SizeLat:36 for: %v8i32 = icmp slt <8 x i32> undef, undef
; CHECK-NEXT: Cost Model: Found costs of RThru:72 CodeSize:68 Lat:72 SizeLat:72 for: %v16i32 = icmp slt <16 x i32> undef, undef
-; CHECK-NEXT: Cost Model: Found costs of RThru:36 CodeSize:18 Lat:36 SizeLat:36 for: %v2i64 = icmp slt <2 x i64> undef, undef
-; CHECK-NEXT: Cost Model: Found costs of RThru:72 CodeSize:36 Lat:72 SizeLat:72 for: %v4i64 = icmp slt <4 x i64> undef, undef
-; CHECK-NEXT: Cost Model: Found costs of RThru:144 CodeSize:72 Lat:144 SizeLat:144 for: %v8i64 = icmp slt <8 x i64> undef, undef
-; CHECK-NEXT: Cost Model: Found costs of RThru:68 CodeSize:34 Lat:68 SizeLat:68 for: %v2i128 = icmp slt <2 x i128> undef, undef
-; CHECK-NEXT: Cost Model: Found costs of RThru:136 CodeSize:68 Lat:136 SizeLat:136 for: %v4i128 = icmp slt <4 x i128> undef, undef
+; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:20 Lat:40 SizeLat:40 for: %v2i64 = icmp slt <2 x i64> undef, undef
+; CHECK-NEXT: Cost Model: Found costs of RThru:80 CodeSize:40 Lat:80 SizeLat:80 for: %v4i64 = icmp slt <4 x i64> undef, undef
+; CHECK-NEXT: Cost Model: Found costs of RThru:160 CodeSize:80 Lat:160 SizeLat:160 for: %v8i64 = icmp slt <8 x i64> undef, undef
+; CHECK-NEXT: Cost Model: Found costs of RThru:80 CodeSize:40 Lat:80 SizeLat:80 for: %v2i128 = icmp slt <2 x i128> undef, undef
+; CHECK-NEXT: Cost Model: Found costs of RThru:160 CodeSize:80 Lat:160 SizeLat:160 for: %v4i128 = icmp slt <4 x i128> undef, undef
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%v2i8 = icmp slt <2 x i8> undef, undef
diff --git a/llvm/test/Analysis/CostModel/ARM/mve-minmax.ll b/llvm/test/Analysis/CostModel/ARM/mve-minmax.ll
index e4cc8fed5052c..fd3ecefda013a 100644
--- a/llvm/test/Analysis/CostModel/ARM/mve-minmax.ll
+++ b/llvm/test/Analysis/CostModel/ARM/mve-minmax.ll
@@ -32,10 +32,10 @@ declare <64 x i8> @llvm.smin.v64i8(<64 x i8>, <64 x i8>)
define i32 @smin(i32 %arg) {
; MVE-LABEL: 'smin'
-; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I64 = call i64 @llvm.smin.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:38 CodeSize:19 Lat:38 SizeLat:38 for: %V2I64 = call <2 x i64> @llvm.smin.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:76 CodeSize:38 Lat:76 SizeLat:76 for: %V4I64 = call <4 x i64> @llvm.smin.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:152 CodeSize:76 Lat:152 SizeLat:152 for: %V8I64 = call <8 x i64> @llvm.smin.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:4 SizeLat:4 for: %I64 = call i64 @llvm.smin.i64(i64 undef, i64 undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:42 CodeSize:21 Lat:42 SizeLat:42 for: %V2I64 = call <2 x i64> @llvm.smin.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:84 CodeSize:42 Lat:84 SizeLat:84 for: %V4I64 = call <4 x i64> @llvm.smin.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:168 CodeSize:84 Lat:168 SizeLat:168 for: %V8I64 = call <8 x i64> @llvm.smin.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %I32 = call i32 @llvm.smin.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:22 CodeSize:11 Lat:22 SizeLat:22 for: %V2I32 = call <2 x i32> @llvm.smin.v2i32(<2 x i32> undef, <2 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> undef, <4 x i32> undef)
@@ -114,10 +114,10 @@ declare <64 x i8> @llvm.smax.v64i8(<64 x i8>, <64 x i8>)
define i32 @smax(i32 %arg) {
; MVE-LABEL: 'smax'
-; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I64 = call i64 @llvm.smax.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:38 CodeSize:19 Lat:38 SizeLat:38 for: %V2I64 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:76 CodeSize:38 Lat:76 SizeLat:76 for: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:152 CodeSize:76 Lat:152 SizeLat:152 for: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:4 SizeLat:4 for: %I64 = call i64 @llvm.smax.i64(i64 undef, i64 undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:42 CodeSize:21 Lat:42 SizeLat:42 for: %V2I64 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:84 CodeSize:42 Lat:84 SizeLat:84 for: %V4I64 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:168 CodeSize:84 Lat:168 SizeLat:168 for: %V8I64 = call <8 x i64> @llvm.smax.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %I32 = call i32 @llvm.smax.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:22 CodeSize:11 Lat:22 SizeLat:22 for: %V2I32 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> undef, <2 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> undef, <4 x i32> undef)
@@ -197,10 +197,10 @@ declare <64 x i8> @llvm.umin.v64i8(<64 x i8>, <64 x i8>)
define i32 @umin(i32 %arg) {
; MVE-LABEL: 'umin'
-; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I64 = call i64 @llvm.umin.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:38 CodeSize:19 Lat:38 SizeLat:38 for: %V2I64 = call <2 x i64> @llvm.umin.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:76 CodeSize:38 Lat:76 SizeLat:76 for: %V4I64 = call <4 x i64> @llvm.umin.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:152 CodeSize:76 Lat:152 SizeLat:152 for: %V8I64 = call <8 x i64> @llvm.umin.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:4 SizeLat:4 for: %I64 = call i64 @llvm.umin.i64(i64 undef, i64 undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:42 CodeSize:21 Lat:42 SizeLat:42 for: %V2I64 = call <2 x i64> @llvm.umin.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:84 CodeSize:42 Lat:84 SizeLat:84 for: %V4I64 = call <4 x i64> @llvm.umin.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:168 CodeSize:84 Lat:168 SizeLat:168 for: %V8I64 = call <8 x i64> @llvm.umin.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %I32 = call i32 @llvm.umin.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:22 CodeSize:11 Lat:22 SizeLat:22 for: %V2I32 = call <2 x i32> @llvm.umin.v2i32(<2 x i32> undef, <2 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> undef, <4 x i32> undef)
@@ -279,10 +279,10 @@ declare <64 x i8> @llvm.umax.v64i8(<64 x i8>, <64 x i8>)
define i32 @umax(i32 %arg) {
; MVE-LABEL: 'umax'
-; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I64 = call i64 @llvm.umax.i64(i64 undef, i64 undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:38 CodeSize:19 Lat:38 SizeLat:38 for: %V2I64 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> undef, <2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:76 CodeSize:38 Lat:76 SizeLat:76 for: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:152 CodeSize:76 Lat:152 SizeLat:152 for: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:4 SizeLat:4 for: %I64 = call i64 @llvm.umax.i64(i64 undef, i64 undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:42 CodeSize:21 Lat:42 SizeLat:42 for: %V2I64 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> undef, <2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:84 CodeSize:42 Lat:84 SizeLat:84 for: %V4I64 = call <4 x i64> @llvm.umax.v4i64(<4 x i64> undef, <4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:168 CodeSize:84 Lat:168 SizeLat:168 for: %V8I64 = call <8 x i64> @llvm.umax.v8i64(<8 x i64> undef, <8 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:3 Lat:2 SizeLat:2 for: %I32 = call i32 @llvm.umax.i32(i32 undef, i32 undef)
; MVE-NEXT: Cost Model: Found costs of RThru:22 CodeSize:11 Lat:22 SizeLat:22 for: %V2I32 = call <2 x i32> @llvm.umax.v2i32(<2 x i32> undef, <2 x i32> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.umax.v4i32(<4 x i32> undef, <4 x i32> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/reduce-and.ll b/llvm/test/Analysis/CostModel/ARM/reduce-and.ll
index 8a4407b361909..3610941401428 100644
--- a/llvm/test/Analysis/CostModel/ARM/reduce-and.ll
+++ b/llvm/test/Analysis/CostModel/ARM/reduce-and.ll
@@ -13,8 +13,8 @@ define i32 @reduce_i1(i32 %arg) {
; V8M-NEXT: Cost Model: Found costs of RThru:9 CodeSize:2 Lat:2 SizeLat:2 for: %V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:17 CodeSize:2 Lat:2 SizeLat:2 for: %V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:33 CodeSize:2 Lat:2 SizeLat:2 for: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:65 CodeSize:2 Lat:2 SizeLat:2 for: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:129 CodeSize:2 Lat:2 SizeLat:2 for: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:66 CodeSize:3 Lat:3 SizeLat:3 for: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:132 CodeSize:5 Lat:5 SizeLat:5 for: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'reduce_i1'
@@ -24,8 +24,8 @@ define i32 @reduce_i1(i32 %arg) {
; NEON-NEXT: Cost Model: Found costs of 2 for: %V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
; NEON-NEXT: Cost Model: Found costs of 2 for: %V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
; NEON-NEXT: Cost Model: Found costs of RThru:97 CodeSize:2 Lat:2 SizeLat:2 for: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
-; NEON-NEXT: Cost Model: Found costs of RThru:193 CodeSize:2 Lat:2 SizeLat:2 for: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
-; NEON-NEXT: Cost Model: Found costs of RThru:385 CodeSize:2 Lat:2 SizeLat:2 for: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
+; NEON-NEXT: Cost Model: Found costs of RThru:194 CodeSize:3 Lat:3 SizeLat:3 for: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
+; NEON-NEXT: Cost Model: Found costs of RThru:388 CodeSize:5 Lat:5 SizeLat:5 for: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
; NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; MVE-LABEL: 'reduce_i1'
@@ -35,8 +35,8 @@ define i32 @reduce_i1(i32 %arg) {
; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:2 SizeLat:2 for: %V8 = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:2 SizeLat:2 for: %V16 = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:257 CodeSize:2 Lat:2 SizeLat:2 for: %V32 = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:513 CodeSize:2 Lat:2 SizeLat:2 for: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:1025 CodeSize:2 Lat:2 SizeLat:2 for: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:514 CodeSize:3 Lat:3 SizeLat:3 for: %V64 = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:1028 CodeSize:5 Lat:5 SizeLat:5 for: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/reduce-or.ll b/llvm/test/Analysis/CostModel/ARM/reduce-or.ll
index 05df62d2131b0..5234f68bc5879 100644
--- a/llvm/test/Analysis/CostModel/ARM/reduce-or.ll
+++ b/llvm/test/Analysis/CostModel/ARM/reduce-or.ll
@@ -13,8 +13,8 @@ define i32 @reduce_i1(i32 %arg) {
; V8M-NEXT: Cost Model: Found costs of RThru:9 CodeSize:2 Lat:2 SizeLat:2 for: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:17 CodeSize:2 Lat:2 SizeLat:2 for: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
; V8M-NEXT: Cost Model: Found costs of RThru:33 CodeSize:2 Lat:2 SizeLat:2 for: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:65 CodeSize:2 Lat:2 SizeLat:2 for: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:129 CodeSize:2 Lat:2 SizeLat:2 for: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:66 CodeSize:3 Lat:3 SizeLat:3 for: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:132 CodeSize:5 Lat:5 SizeLat:5 for: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'reduce_i1'
@@ -24,8 +24,8 @@ define i32 @reduce_i1(i32 %arg) {
; NEON-NEXT: Cost Model: Found costs of 2 for: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
; NEON-NEXT: Cost Model: Found costs of 2 for: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
; NEON-NEXT: Cost Model: Found costs of RThru:97 CodeSize:2 Lat:2 SizeLat:2 for: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
-; NEON-NEXT: Cost Model: Found costs of RThru:193 CodeSize:2 Lat:2 SizeLat:2 for: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
-; NEON-NEXT: Cost Model: Found costs of RThru:385 CodeSize:2 Lat:2 SizeLat:2 for: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
+; NEON-NEXT: Cost Model: Found costs of RThru:194 CodeSize:3 Lat:3 SizeLat:3 for: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
+; NEON-NEXT: Cost Model: Found costs of RThru:388 CodeSize:5 Lat:5 SizeLat:5 for: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
; NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; MVE-LABEL: 'reduce_i1'
@@ -35,8 +35,8 @@ define i32 @reduce_i1(i32 %arg) {
; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:2 SizeLat:2 for: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:2 Lat:2 SizeLat:2 for: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:257 CodeSize:2 Lat:2 SizeLat:2 for: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:513 CodeSize:2 Lat:2 SizeLat:2 for: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:1025 CodeSize:2 Lat:2 SizeLat:2 for: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:514 CodeSize:3 Lat:3 SizeLat:3 for: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:1028 CodeSize:5 Lat:5 SizeLat:5 for: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/reduce-smax.ll b/llvm/test/Analysis/CostModel/ARM/reduce-smax.ll
index 861d825b3ecdb..b01534d5c25af 100644
--- a/llvm/test/Analysis/CostModel/ARM/reduce-smax.ll
+++ b/llvm/test/Analysis/CostModel/ARM/reduce-smax.ll
@@ -8,10 +8,10 @@ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
define i32 @reduce_i64(i32 %arg) {
; V8M-LABEL: 'reduce_i64'
; V8M-NEXT: Cost Model: Found costs of 2 for: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:13 CodeSize:14 Lat:13 SizeLat:13 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:35 CodeSize:38 Lat:35 SizeLat:35 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:79 CodeSize:86 Lat:79 SizeLat:79 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:167 CodeSize:182 Lat:167 SizeLat:167 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:14 CodeSize:15 Lat:14 SizeLat:14 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:38 CodeSize:41 Lat:38 SizeLat:38 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:86 CodeSize:93 Lat:86 SizeLat:86 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:182 CodeSize:197 Lat:182 SizeLat:182 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'reduce_i64'
@@ -24,10 +24,10 @@ define i32 @reduce_i64(i32 %arg) {
;
; MVE-LABEL: 'reduce_i64'
; MVE-NEXT: Cost Model: Found costs of 8 for: %V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:110 CodeSize:59 Lat:110 SizeLat:110 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:212 CodeSize:110 Lat:212 SizeLat:212 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:416 CodeSize:212 Lat:416 SizeLat:416 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:824 CodeSize:416 Lat:824 SizeLat:824 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:114 CodeSize:61 Lat:114 SizeLat:114 for: %V2 = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:220 CodeSize:114 Lat:220 SizeLat:220 for: %V4 = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:432 CodeSize:220 Lat:432 SizeLat:432 for: %V8 = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:856 CodeSize:432 Lat:856 SizeLat:856 for: %V16 = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/reduce-smin.ll b/llvm/test/Analysis/CostModel/ARM/reduce-smin.ll
index d8fcc7bca9155..e5e1205d99658 100644
--- a/llvm/test/Analysis/CostModel/ARM/reduce-smin.ll
+++ b/llvm/test/Analysis/CostModel/ARM/reduce-smin.ll
@@ -8,10 +8,10 @@ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
define i32 @reduce_i64(i32 %arg) {
; V8M-LABEL: 'reduce_i64'
; V8M-NEXT: Cost Model: Found costs of 2 for: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:13 CodeSize:14 Lat:13 SizeLat:13 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:35 CodeSize:38 Lat:35 SizeLat:35 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:79 CodeSize:86 Lat:79 SizeLat:79 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:167 CodeSize:182 Lat:167 SizeLat:167 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:14 CodeSize:15 Lat:14 SizeLat:14 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:38 CodeSize:41 Lat:38 SizeLat:38 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:86 CodeSize:93 Lat:86 SizeLat:86 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:182 CodeSize:197 Lat:182 SizeLat:182 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'reduce_i64'
@@ -24,10 +24,10 @@ define i32 @reduce_i64(i32 %arg) {
;
; MVE-LABEL: 'reduce_i64'
; MVE-NEXT: Cost Model: Found costs of 8 for: %V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:110 CodeSize:59 Lat:110 SizeLat:110 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:212 CodeSize:110 Lat:212 SizeLat:212 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:416 CodeSize:212 Lat:416 SizeLat:416 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:824 CodeSize:416 Lat:824 SizeLat:824 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:114 CodeSize:61 Lat:114 SizeLat:114 for: %V2 = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:220 CodeSize:114 Lat:220 SizeLat:220 for: %V4 = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:432 CodeSize:220 Lat:432 SizeLat:432 for: %V8 = call i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:856 CodeSize:432 Lat:856 SizeLat:856 for: %V16 = call i64 @llvm.vector.reduce.smin.v16i64(<16 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/reduce-umax.ll b/llvm/test/Analysis/CostModel/ARM/reduce-umax.ll
index b95808a1bb4b5..90e707535f7f7 100644
--- a/llvm/test/Analysis/CostModel/ARM/reduce-umax.ll
+++ b/llvm/test/Analysis/CostModel/ARM/reduce-umax.ll
@@ -8,10 +8,10 @@ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
define i32 @reduce_i64(i32 %arg) {
; V8M-LABEL: 'reduce_i64'
; V8M-NEXT: Cost Model: Found costs of 2 for: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:13 CodeSize:14 Lat:13 SizeLat:13 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:35 CodeSize:38 Lat:35 SizeLat:35 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:79 CodeSize:86 Lat:79 SizeLat:79 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:167 CodeSize:182 Lat:167 SizeLat:167 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:14 CodeSize:15 Lat:14 SizeLat:14 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:38 CodeSize:41 Lat:38 SizeLat:38 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:86 CodeSize:93 Lat:86 SizeLat:86 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:182 CodeSize:197 Lat:182 SizeLat:182 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'reduce_i64'
@@ -24,10 +24,10 @@ define i32 @reduce_i64(i32 %arg) {
;
; MVE-LABEL: 'reduce_i64'
; MVE-NEXT: Cost Model: Found costs of 8 for: %V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:110 CodeSize:59 Lat:110 SizeLat:110 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:212 CodeSize:110 Lat:212 SizeLat:212 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:416 CodeSize:212 Lat:416 SizeLat:416 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:824 CodeSize:416 Lat:824 SizeLat:824 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:114 CodeSize:61 Lat:114 SizeLat:114 for: %V2 = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:220 CodeSize:114 Lat:220 SizeLat:220 for: %V4 = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:432 CodeSize:220 Lat:432 SizeLat:432 for: %V8 = call i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:856 CodeSize:432 Lat:856 SizeLat:856 for: %V16 = call i64 @llvm.vector.reduce.umax.v16i64(<16 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> undef)
diff --git a/llvm/test/Analysis/CostModel/ARM/reduce-umin.ll b/llvm/test/Analysis/CostModel/ARM/reduce-umin.ll
index 055606b0f8617..90dd42f1c2a25 100644
--- a/llvm/test/Analysis/CostModel/ARM/reduce-umin.ll
+++ b/llvm/test/Analysis/CostModel/ARM/reduce-umin.ll
@@ -8,10 +8,10 @@ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
define i32 @reduce_i64(i32 %arg) {
; V8M-LABEL: 'reduce_i64'
; V8M-NEXT: Cost Model: Found costs of 2 for: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:13 CodeSize:14 Lat:13 SizeLat:13 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:35 CodeSize:38 Lat:35 SizeLat:35 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:79 CodeSize:86 Lat:79 SizeLat:79 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
-; V8M-NEXT: Cost Model: Found costs of RThru:167 CodeSize:182 Lat:167 SizeLat:167 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:14 CodeSize:15 Lat:14 SizeLat:14 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:38 CodeSize:41 Lat:38 SizeLat:38 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:86 CodeSize:93 Lat:86 SizeLat:86 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
+; V8M-NEXT: Cost Model: Found costs of RThru:182 CodeSize:197 Lat:182 SizeLat:182 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef
;
; NEON-LABEL: 'reduce_i64'
@@ -24,10 +24,10 @@ define i32 @reduce_i64(i32 %arg) {
;
; MVE-LABEL: 'reduce_i64'
; MVE-NEXT: Cost Model: Found costs of 8 for: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:110 CodeSize:59 Lat:110 SizeLat:110 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:212 CodeSize:110 Lat:212 SizeLat:212 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:416 CodeSize:212 Lat:416 SizeLat:416 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
-; MVE-NEXT: Cost Model: Found costs of RThru:824 CodeSize:416 Lat:824 SizeLat:824 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:114 CodeSize:61 Lat:114 SizeLat:114 for: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:220 CodeSize:114 Lat:220 SizeLat:220 for: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:432 CodeSize:220 Lat:432 SizeLat:432 for: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> undef)
+; MVE-NEXT: Cost Model: Found costs of RThru:856 CodeSize:432 Lat:856 SizeLat:856 for: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> undef)
; MVE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> undef)
diff --git a/llvm/test/CodeGen/ARM/cmp.ll b/llvm/test/CodeGen/ARM/cmp.ll
index f2af6c4b631b0..e213ebb8f8292 100644
--- a/llvm/test/CodeGen/ARM/cmp.ll
+++ b/llvm/test/CodeGen/ARM/cmp.ll
@@ -188,19 +188,19 @@ entry:
define arm_aapcscc i32 @swap_cmp_rotr(i32 %a, i32 %b) {
; CHECK-LABEL: swap_cmp_rotr:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: mov r2, #0
-; CHECK-NEXT: cmp r1, r0, ror #11
-; CHECK-NEXT: movwls r2, #1
-; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: ror r2, r0, #11
+; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: cmp r2, r1
+; CHECK-NEXT: movwhs r0, #1
; CHECK-NEXT: bx lr
;
; CHECK-T2-LABEL: swap_cmp_rotr:
; CHECK-T2: @ %bb.0: @ %entry
-; CHECK-T2-NEXT: movs r2, #0
-; CHECK-T2-NEXT: cmp.w r1, r0, ror #11
-; CHECK-T2-NEXT: it ls
-; CHECK-T2-NEXT: movls r2, #1
-; CHECK-T2-NEXT: mov r0, r2
+; CHECK-T2-NEXT: ror.w r2, r0, #11
+; CHECK-T2-NEXT: movs r0, #0
+; CHECK-T2-NEXT: cmp r2, r1
+; CHECK-T2-NEXT: it hs
+; CHECK-T2-NEXT: movhs r0, #1
; CHECK-T2-NEXT: bx lr
entry:
%lsr = lshr i32 %a, 11
diff --git a/llvm/test/CodeGen/ARM/umulo-32.ll b/llvm/test/CodeGen/ARM/umulo-32.ll
index cd0d784c89818..bdf471b5c358c 100644
--- a/llvm/test/CodeGen/ARM/umulo-32.ll
+++ b/llvm/test/CodeGen/ARM/umulo-32.ll
@@ -31,14 +31,11 @@ define i32 @test2(ptr %m_degree) ssp {
; CHECK-LABEL: test2:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r4, lr}
+; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: ldr r1, [r0]
; CHECK-NEXT: lsls r0, r1, #3
; CHECK-NEXT: lsrs r2, r0, #3
-; CHECK-NEXT: subs r1, r2, r1
-; CHECK-NEXT: subs r2, r1, #1
-; CHECK-NEXT: sbcs r1, r2
-; CHECK-NEXT: movs r4, #0
-; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: cmp r1, r2
; CHECK-NEXT: beq .LBB1_2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: mvns r0, r4
diff --git a/llvm/test/CodeGen/Thumb/smul_fix_sat.ll b/llvm/test/CodeGen/Thumb/smul_fix_sat.ll
index 52921f0f347b9..dbff58806284d 100644
--- a/llvm/test/CodeGen/Thumb/smul_fix_sat.ll
+++ b/llvm/test/CodeGen/Thumb/smul_fix_sat.ll
@@ -456,7 +456,7 @@ define i64 @func7(i64 %x, i64 %y) nounwind {
; ARM-NEXT: adcs r7, r2
; ARM-NEXT: cmp r3, #0
; ARM-NEXT: mov r3, r0
-; ARM-NEXT: bge .LBB6_8
+; ARM-NEXT: bpl .LBB6_8
; ARM-NEXT: @ %bb.7:
; ARM-NEXT: mov r3, r4
; ARM-NEXT: .LBB6_8:
diff --git a/llvm/test/CodeGen/Thumb2/float-cmp.ll b/llvm/test/CodeGen/Thumb2/float-cmp.ll
index 03a176cde278c..b918e5a069193 100644
--- a/llvm/test/CodeGen/Thumb2/float-cmp.ll
+++ b/llvm/test/CodeGen/Thumb2/float-cmp.ll
@@ -524,9 +524,7 @@ define i1 @cmp_d_one(double %a, double %b) {
; SP-NEXT: bl __aeabi_dcmpeq
; SP-NEXT: clz r0, r0
; SP-NEXT: lsrs r0, r0, #5
-; SP-NEXT: ands.w r0, r0, r8
-; SP-NEXT: it ne
-; SP-NEXT: movne r0, #1
+; SP-NEXT: and.w r0, r0, r8
; SP-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
%1 = fcmp one double %a, %b
@@ -683,8 +681,6 @@ define i1 @cmp_d_ueq(double %a, double %b) {
; SP-NEXT: it ne
; SP-NEXT: movne r0, #1
; SP-NEXT: orrs r0, r7
-; SP-NEXT: it ne
-; SP-NEXT: movne r0, #1
; SP-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
%1 = fcmp ueq double %a, %b
ret i1 %1
diff --git a/llvm/test/CodeGen/Thumb2/mve-no-fp.ll b/llvm/test/CodeGen/Thumb2/mve-no-fp.ll
index 941c1772e5e53..9c98a4a9b7014 100644
--- a/llvm/test/CodeGen/Thumb2/mve-no-fp.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-no-fp.ll
@@ -9,15 +9,15 @@ define i32 @fptosi_sat_i32_f32(float %x) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr}
-; CHECK-NEXT: ldr r1, .LCPI0_0
+; CHECK-NEXT: mov.w r1, #-822083584
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: bl __aeabi_fcmpge
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: bl __aeabi_f2iz
-; CHECK-NEXT: ldr r1, .LCPI0_1
; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mvn r1, #-1325400064
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r6, #-2147483648
@@ -33,12 +33,6 @@ define i32 @fptosi_sat_i32_f32(float %x) {
; CHECK-NEXT: movne r6, #0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: pop {r4, r5, r6, pc}
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI0_0:
-; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9
-; CHECK-NEXT: .LCPI0_1:
-; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9
%i = call i32 @llvm.fptosi.sat.i32.f32(float %x)
ret i32 %i
}
@@ -48,15 +42,16 @@ define i32 @fptoui_sat_i32_f32(float %x) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr}
-; CHECK-NEXT: ldr r1, .LCPI1_0
+; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: bl __aeabi_fcmpge
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: bl __aeabi_f2uiz
-; CHECK-NEXT: ldr r1, .LCPI1_1
; CHECK-NEXT: cmp r5, #0
+; CHECK-NEXT: movw r1, #65535
; CHECK-NEXT: csel r5, r0, r5, ne
+; CHECK-NEXT: movt r1, #20351
; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: bl __aeabi_fcmpgt
; CHECK-NEXT: cmp r0, #0
@@ -64,12 +59,6 @@ define i32 @fptoui_sat_i32_f32(float %x) {
; CHECK-NEXT: movne.w r5, #-1
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: pop {r4, r5, r7, pc}
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI1_0:
-; CHECK-NEXT: .long 0x00000000 @ float 0
-; CHECK-NEXT: .LCPI1_1:
-; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9
%i = call i32 @llvm.fptoui.sat.i32.f32(float %x)
ret i32 %i
}
@@ -218,24 +207,22 @@ define i64 @fptosu_sat_i64_f64(double %x) {
define <4 x i32> @fptosi_sat_v4i32_v4f32(<4 x float> %x) {
; CHECK-LABEL: fptosi_sat_v4i32_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: mov r10, r3
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: mov r8, r3
; CHECK-NEXT: mov r6, r2
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: bl __aeabi_f2iz
-; CHECK-NEXT: ldr.w r8, .LCPI4_0
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r7
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov.w r1, #-822083584
; CHECK-NEXT: bl __aeabi_fcmpge
-; CHECK-NEXT: ldr.w r9, .LCPI4_1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mvn r1, #-1325400064
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r5, #-2147483648
-; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: bl __aeabi_fcmpgt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r7
@@ -250,11 +237,11 @@ define <4 x i32> @fptosi_sat_v4i32_v4f32(<4 x float> %x) {
; CHECK-NEXT: bl __aeabi_f2iz
; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov.w r1, #-822083584
; CHECK-NEXT: bl __aeabi_fcmpge
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mvn r1, #-1325400064
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r7, #-2147483648
; CHECK-NEXT: bl __aeabi_fcmpgt
@@ -271,11 +258,11 @@ define <4 x i32> @fptosi_sat_v4i32_v4f32(<4 x float> %x) {
; CHECK-NEXT: bl __aeabi_f2iz
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov.w r1, #-822083584
; CHECK-NEXT: bl __aeabi_fcmpge
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mvn r1, #-1325400064
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r4, #-2147483648
; CHECK-NEXT: bl __aeabi_fcmpgt
@@ -286,23 +273,23 @@ define <4 x i32> @fptosi_sat_v4i32_v4f32(<4 x float> %x) {
; CHECK-NEXT: mvnne r4, #-2147483648
; CHECK-NEXT: bl __aeabi_fcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: bl __aeabi_f2iz
; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: mov r0, r10
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov.w r1, #-822083584
; CHECK-NEXT: bl __aeabi_fcmpge
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r10
-; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mvn r1, #-1325400064
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r6, #-2147483648
; CHECK-NEXT: bl __aeabi_fcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r10
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r6, #-2147483648
; CHECK-NEXT: bl __aeabi_fcmpun
@@ -313,13 +300,7 @@ define <4 x i32> @fptosi_sat_v4i32_v4f32(<4 x float> %x) {
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r4
; CHECK-NEXT: mov r3, r6
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI4_0:
-; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9
-; CHECK-NEXT: .LCPI4_1:
-; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
%i = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %x)
ret <4 x i32> %i
}
diff --git a/llvm/test/Transforms/LoopUnroll/ARM/unroll-optsize.ll b/llvm/test/Transforms/LoopUnroll/ARM/unroll-optsize.ll
index c2bba9426e64c..853504da57ce7 100644
--- a/llvm/test/Transforms/LoopUnroll/ARM/unroll-optsize.ll
+++ b/llvm/test/Transforms/LoopUnroll/ARM/unroll-optsize.ll
@@ -16,7 +16,7 @@ define void @fully_unrolled_single_iteration(ptr %src) #0 {
; CHECK-NEXT: [[ARR:%.*]] = alloca [4 x i32], align 4
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[SRC:%.*]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[SRC:%.*]], align 4
; CHECK-NEXT: store i32 [[V]], ptr [[ARR]], align 4
; CHECK-NEXT: call void @use(ptr nonnull [[ARR]])
; CHECK-NEXT: ret void
@@ -122,17 +122,21 @@ define void @fully_unrolled_bigger() #0 {
; CHECK-NEXT: [[ARR:%.*]] = alloca [4 x i32], align 4
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[INDVARS_IV_TR:%.*]] = trunc i64 [[INDVARS_IV]] to i32
-; CHECK-NEXT: [[SHL_0:%.*]] = shl i32 [[INDVARS_IV_TR]], 3
-; CHECK-NEXT: [[SHL_1:%.*]] = shl i32 16, [[SHL_0]]
-; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL_1]], [[SHL_0]]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 [[INDVARS_IV]]
-; CHECK-NEXT: store i32 [[OR]], ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV]], 7
-; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]]
-; CHECK: for.cond.cleanup:
+; CHECK-NEXT: store i32 16, ptr [[ARR]], align 4
+; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 1
+; CHECK-NEXT: store i32 4104, ptr [[ARRAYIDX_1]], align 4
+; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 2
+; CHECK-NEXT: store i32 1048592, ptr [[ARRAYIDX_2]], align 4
+; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 3
+; CHECK-NEXT: store i32 268435480, ptr [[ARRAYIDX_3]], align 4
+; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 4
+; CHECK-NEXT: store i32 poison, ptr [[ARRAYIDX_4]], align 4
+; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 5
+; CHECK-NEXT: store i32 poison, ptr [[ARRAYIDX_5]], align 4
+; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 6
+; CHECK-NEXT: store i32 poison, ptr [[ARRAYIDX_6]], align 4
+; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 7
+; CHECK-NEXT: store i32 poison, ptr [[ARRAYIDX_7]], align 4
; CHECK-NEXT: call void @use(ptr nonnull [[ARR]])
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll b/llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
index 83be0708774f1..2526acdb47079 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll
@@ -181,24 +181,137 @@ for.cond.cleanup:
define void @tail_predicate_without_optsize(ptr %p, i8 %a, i8 %b, i8 %c, i32 %n) {
; DEFAULT-LABEL: define void @tail_predicate_without_optsize(
; DEFAULT-SAME: ptr [[P:%.*]], i8 [[A:%.*]], i8 [[B:%.*]], i8 [[C:%.*]], i32 [[N:%.*]]) {
-; DEFAULT-NEXT: [[ENTRY:.*]]:
+; DEFAULT-NEXT: [[ENTRY:.*:]]
; DEFAULT-NEXT: br label %[[FOR_BODY:.*]]
; DEFAULT: [[FOR_BODY]]:
-; DEFAULT-NEXT: [[TMP69:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
-; DEFAULT-NEXT: [[TMP0:%.*]] = trunc nuw nsw i64 [[TMP69]] to i8
-; DEFAULT-NEXT: [[MUL:%.*]] = mul i8 [[A]], [[TMP0]]
-; DEFAULT-NEXT: [[SHR:%.*]] = lshr i8 [[TMP0]], 1
-; DEFAULT-NEXT: [[MUL5:%.*]] = mul i8 [[SHR]], [[B]]
-; DEFAULT-NEXT: [[ADD:%.*]] = add i8 [[MUL5]], [[MUL]]
-; DEFAULT-NEXT: [[SHR7:%.*]] = lshr i8 [[TMP0]], 2
-; DEFAULT-NEXT: [[MUL9:%.*]] = mul i8 [[SHR7]], [[C]]
-; DEFAULT-NEXT: [[TMP71:%.*]] = add i8 [[ADD]], [[MUL9]]
-; DEFAULT-NEXT: [[TMP70:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[TMP69]]
+; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[A]], i64 0
+; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer
+; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <16 x i8> poison, i8 [[B]], i64 0
+; DEFAULT-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT1]], <16 x i8> poison, <16 x i32> zeroinitializer
+; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <16 x i8> poison, i8 [[C]], i64 0
+; DEFAULT-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT3]], <16 x i8> poison, <16 x i32> zeroinitializer
+; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]
+; DEFAULT: [[VECTOR_BODY]]:
+; DEFAULT-NEXT: [[TMP0:%.*]] = mul <16 x i8> [[BROADCAST_SPLAT]], <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>
+; DEFAULT-NEXT: [[TMP1:%.*]] = mul <16 x i8> <i8 0, i8 0, i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7>, [[BROADCAST_SPLAT2]]
+; DEFAULT-NEXT: [[TMP2:%.*]] = add <16 x i8> [[TMP1]], [[TMP0]]
+; DEFAULT-NEXT: [[TMP3:%.*]] = mul <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 2, i8 2, i8 2, i8 2, i8 3, i8 3, i8 3, i8 3>, [[BROADCAST_SPLAT4]]
+; DEFAULT-NEXT: [[TMP4:%.*]] = add <16 x i8> [[TMP2]], [[TMP3]]
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
+; DEFAULT: [[PRED_STORE_IF]]:
+; DEFAULT-NEXT: [[TMP5:%.*]] = extractelement <16 x i8> [[TMP4]], i64 0
+; DEFAULT-NEXT: store i8 [[TMP5]], ptr [[P]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE]]
+; DEFAULT: [[PRED_STORE_CONTINUE]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF5:.*]], label %[[FOR_COND_CLEANUP:.*]]
+; DEFAULT: [[PRED_STORE_IF5]]:
+; DEFAULT-NEXT: [[TMP70:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 1
+; DEFAULT-NEXT: [[TMP71:%.*]] = extractelement <16 x i8> [[TMP4]], i64 1
; DEFAULT-NEXT: store i8 [[TMP71]], ptr [[TMP70]], align 1
-; DEFAULT-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[TMP69]], 1
-; DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 15
-; DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP:.*]], label %[[FOR_BODY]]
+; DEFAULT-NEXT: br label %[[FOR_COND_CLEANUP]]
; DEFAULT: [[FOR_COND_CLEANUP]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]
+; DEFAULT: [[PRED_STORE_IF7]]:
+; DEFAULT-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 2
+; DEFAULT-NEXT: [[TMP9:%.*]] = extractelement <16 x i8> [[TMP4]], i64 2
+; DEFAULT-NEXT: store i8 [[TMP9]], ptr [[TMP8]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE8]]
+; DEFAULT: [[PRED_STORE_CONTINUE8]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]
+; DEFAULT: [[PRED_STORE_IF9]]:
+; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 3
+; DEFAULT-NEXT: [[TMP11:%.*]] = extractelement <16 x i8> [[TMP4]], i64 3
+; DEFAULT-NEXT: store i8 [[TMP11]], ptr [[TMP10]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE10]]
+; DEFAULT: [[PRED_STORE_CONTINUE10]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]
+; DEFAULT: [[PRED_STORE_IF11]]:
+; DEFAULT-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 4
+; DEFAULT-NEXT: [[TMP13:%.*]] = extractelement <16 x i8> [[TMP4]], i64 4
+; DEFAULT-NEXT: store i8 [[TMP13]], ptr [[TMP12]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE12]]
+; DEFAULT: [[PRED_STORE_CONTINUE12]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]
+; DEFAULT: [[PRED_STORE_IF13]]:
+; DEFAULT-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 5
+; DEFAULT-NEXT: [[TMP15:%.*]] = extractelement <16 x i8> [[TMP4]], i64 5
+; DEFAULT-NEXT: store i8 [[TMP15]], ptr [[TMP14]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE14]]
+; DEFAULT: [[PRED_STORE_CONTINUE14]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]
+; DEFAULT: [[PRED_STORE_IF15]]:
+; DEFAULT-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 6
+; DEFAULT-NEXT: [[TMP17:%.*]] = extractelement <16 x i8> [[TMP4]], i64 6
+; DEFAULT-NEXT: store i8 [[TMP17]], ptr [[TMP16]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE16]]
+; DEFAULT: [[PRED_STORE_CONTINUE16]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18:.*]]
+; DEFAULT: [[PRED_STORE_IF17]]:
+; DEFAULT-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 7
+; DEFAULT-NEXT: [[TMP19:%.*]] = extractelement <16 x i8> [[TMP4]], i64 7
+; DEFAULT-NEXT: store i8 [[TMP19]], ptr [[TMP18]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE18]]
+; DEFAULT: [[PRED_STORE_CONTINUE18]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF19:.*]], label %[[PRED_STORE_CONTINUE20:.*]]
+; DEFAULT: [[PRED_STORE_IF19]]:
+; DEFAULT-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 8
+; DEFAULT-NEXT: [[TMP21:%.*]] = extractelement <16 x i8> [[TMP4]], i64 8
+; DEFAULT-NEXT: store i8 [[TMP21]], ptr [[TMP20]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE20]]
+; DEFAULT: [[PRED_STORE_CONTINUE20]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF21:.*]], label %[[PRED_STORE_CONTINUE22:.*]]
+; DEFAULT: [[PRED_STORE_IF21]]:
+; DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 9
+; DEFAULT-NEXT: [[TMP23:%.*]] = extractelement <16 x i8> [[TMP4]], i64 9
+; DEFAULT-NEXT: store i8 [[TMP23]], ptr [[TMP22]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE22]]
+; DEFAULT: [[PRED_STORE_CONTINUE22]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF23:.*]], label %[[PRED_STORE_CONTINUE24:.*]]
+; DEFAULT: [[PRED_STORE_IF23]]:
+; DEFAULT-NEXT: [[TMP24:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 10
+; DEFAULT-NEXT: [[TMP25:%.*]] = extractelement <16 x i8> [[TMP4]], i64 10
+; DEFAULT-NEXT: store i8 [[TMP25]], ptr [[TMP24]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE24]]
+; DEFAULT: [[PRED_STORE_CONTINUE24]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF25:.*]], label %[[PRED_STORE_CONTINUE26:.*]]
+; DEFAULT: [[PRED_STORE_IF25]]:
+; DEFAULT-NEXT: [[TMP26:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 11
+; DEFAULT-NEXT: [[TMP27:%.*]] = extractelement <16 x i8> [[TMP4]], i64 11
+; DEFAULT-NEXT: store i8 [[TMP27]], ptr [[TMP26]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE26]]
+; DEFAULT: [[PRED_STORE_CONTINUE26]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF27:.*]], label %[[PRED_STORE_CONTINUE28:.*]]
+; DEFAULT: [[PRED_STORE_IF27]]:
+; DEFAULT-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 12
+; DEFAULT-NEXT: [[TMP29:%.*]] = extractelement <16 x i8> [[TMP4]], i64 12
+; DEFAULT-NEXT: store i8 [[TMP29]], ptr [[TMP28]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE28]]
+; DEFAULT: [[PRED_STORE_CONTINUE28]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF29:.*]], label %[[PRED_STORE_CONTINUE30:.*]]
+; DEFAULT: [[PRED_STORE_IF29]]:
+; DEFAULT-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 13
+; DEFAULT-NEXT: [[TMP31:%.*]] = extractelement <16 x i8> [[TMP4]], i64 13
+; DEFAULT-NEXT: store i8 [[TMP31]], ptr [[TMP30]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE30]]
+; DEFAULT: [[PRED_STORE_CONTINUE30]]:
+; DEFAULT-NEXT: br i1 true, label %[[PRED_STORE_IF31:.*]], label %[[PRED_STORE_CONTINUE32:.*]]
+; DEFAULT: [[PRED_STORE_IF31]]:
+; DEFAULT-NEXT: [[TMP32:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 14
+; DEFAULT-NEXT: [[TMP33:%.*]] = extractelement <16 x i8> [[TMP4]], i64 14
+; DEFAULT-NEXT: store i8 [[TMP33]], ptr [[TMP32]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE32]]
+; DEFAULT: [[PRED_STORE_CONTINUE32]]:
+; DEFAULT-NEXT: br i1 false, label %[[PRED_STORE_IF33:.*]], label %[[PRED_STORE_CONTINUE34:.*]]
+; DEFAULT: [[PRED_STORE_IF33]]:
+; DEFAULT-NEXT: [[TMP34:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 15
+; DEFAULT-NEXT: [[TMP35:%.*]] = extractelement <16 x i8> [[TMP4]], i64 15
+; DEFAULT-NEXT: store i8 [[TMP35]], ptr [[TMP34]], align 1
+; DEFAULT-NEXT: br label %[[PRED_STORE_CONTINUE34]]
+; DEFAULT: [[PRED_STORE_CONTINUE34]]:
+; DEFAULT-NEXT: br label %[[MIDDLE_BLOCK:.*]]
+; DEFAULT: [[MIDDLE_BLOCK]]:
+; DEFAULT-NEXT: br label %[[FOR_COND_CLEANUP1:.*]]
+; DEFAULT: [[FOR_COND_CLEANUP1]]:
; DEFAULT-NEXT: ret void
;
; OPTSIZE-LABEL: define void @tail_predicate_without_optsize(
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