[llvm] Add intrinsics support in narrow interleave group (PR #206455)
Kamlesh Kumar via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 11:49:42 PDT 2026
https://github.com/kamleshbhalui updated https://github.com/llvm/llvm-project/pull/206455
>From 772e7c3c5d181211a9a9efcac38dcd791012af06 Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Mon, 13 Jul 2026 12:18:18 +0000
Subject: [PATCH 1/2] [Test] Added a test
---
...w-interleave-to-widen-memory-intrinsics.ll | 438 ++++++++++++++++++
...w-interleave-to-widen-memory-intrinsics.ll | 62 +++
2 files changed, 500 insertions(+)
create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll
create mode 100644 llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory-intrinsics.ll
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll
new file mode 100644
index 0000000000000..626a8212adfe0
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll
@@ -0,0 +1,438 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -p loop-vectorize -S -force-vector-interleave=1 %s | FileCheck %s
+
+target triple = "arm64-apple-macosx"
+
+define void @powi_two_fields_same_exponent(ptr noalias %src, ptr noalias %dst, i64 %n) {
+; CHECK-LABEL: define void @powi_two_fields_same_exponent(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH1:.*]]
+; CHECK: [[VECTOR_PH1]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x double>, ptr [[TMP0]], align 8
+; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[STRIDED_VEC]], i32 2)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[STRIDED_VEC1]], i32 2)
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP4]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP6]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1]]
+; CHECK: [[SCALAR_PH1]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SRC_0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 0
+; CHECK-NEXT: [[X0:%.*]] = load double, ptr [[SRC_0]], align 8
+; CHECK-NEXT: [[P0:%.*]] = call double @llvm.powi.f64.i32(double [[X0]], i32 2)
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 0
+; CHECK-NEXT: store double [[P0]], ptr [[TMP2]], align 8
+; CHECK-NEXT: [[SRC_1:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 1
+; CHECK-NEXT: [[X1:%.*]] = load double, ptr [[SRC_1]], align 8
+; CHECK-NEXT: [[P1:%.*]] = call double @llvm.powi.f64.i32(double [[X1]], i32 2)
+; CHECK-NEXT: [[DST_1:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 1
+; CHECK-NEXT: store double [[P1]], ptr [[DST_1]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[DONE]], label %[[SCALAR_PH]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %src.0 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 0
+ %x0 = load double, ptr %src.0, align 8
+ %p0 = call double @llvm.powi.f64.i32(double %x0, i32 2)
+ %dst.0 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 0
+ store double %p0, ptr %dst.0, align 8
+ %src.1 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 1
+ %x1 = load double, ptr %src.1, align 8
+ %p1 = call double @llvm.powi.f64.i32(double %x1, i32 2)
+ %dst.1 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 1
+ store double %p1, ptr %dst.1, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, %n
+ br i1 %done, label %exit, label %loop
+exit:
+ ret void
+}
+
+
+define void @powi_two_fields_different_exponent(ptr noalias %src, ptr noalias %dst, i64 %n) {
+; CHECK-LABEL: define void @powi_two_fields_different_exponent(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH1:.*]]
+; CHECK: [[VECTOR_PH1]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x double>, ptr [[TMP0]], align 8
+; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[STRIDED_VEC]], i32 2)
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[STRIDED_VEC1]], i32 3)
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP4]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP6]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1]]
+; CHECK: [[SCALAR_PH1]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SRC_0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 0
+; CHECK-NEXT: [[X0:%.*]] = load double, ptr [[SRC_0]], align 8
+; CHECK-NEXT: [[P0:%.*]] = call double @llvm.powi.f64.i32(double [[X0]], i32 2)
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 0
+; CHECK-NEXT: store double [[P0]], ptr [[TMP2]], align 8
+; CHECK-NEXT: [[SRC_1:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 1
+; CHECK-NEXT: [[X1:%.*]] = load double, ptr [[SRC_1]], align 8
+; CHECK-NEXT: [[P1:%.*]] = call double @llvm.powi.f64.i32(double [[X1]], i32 3)
+; CHECK-NEXT: [[DST_1:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 1
+; CHECK-NEXT: store double [[P1]], ptr [[DST_1]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[DONE]], label %[[SCALAR_PH]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %src.0 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 0
+ %x0 = load double, ptr %src.0, align 8
+ %p0 = call double @llvm.powi.f64.i32(double %x0, i32 2)
+ %dst.0 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 0
+ store double %p0, ptr %dst.0, align 8
+ %src.1 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 1
+ %x1 = load double, ptr %src.1, align 8
+ %p1 = call double @llvm.powi.f64.i32(double %x1, i32 3)
+ %dst.1 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 1
+ store double %p1, ptr %dst.1, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, %n
+ br i1 %done, label %exit, label %loop
+exit:
+ ret void
+}
+
+
+define void @pow_two_fields_two_vector_operands(ptr noalias %lhs, ptr noalias %rhs, ptr noalias %dst, i64 %n) {
+; CHECK-LABEL: define void @pow_two_fields_two_vector_operands(
+; CHECK-SAME: ptr noalias [[LHS:%.*]], ptr noalias [[RHS:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH1:.*]]
+; CHECK: [[VECTOR_PH1]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds { double, double }, ptr [[LHS]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x double>, ptr [[TMP0]], align 8
+; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { double, double }, ptr [[RHS]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <4 x double>, ptr [[TMP7]], align 8
+; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x double> [[WIDE_VEC2]], <4 x double> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x double> [[WIDE_VEC2]], <4 x double> poison, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> [[STRIDED_VEC]], <2 x double> [[STRIDED_VEC3]])
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> [[STRIDED_VEC1]], <2 x double> [[STRIDED_VEC4]])
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP8]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1]]
+; CHECK: [[SCALAR_PH1]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[LHS_0:%.*]] = getelementptr inbounds { double, double }, ptr [[LHS]], i64 [[IV]], i32 0
+; CHECK-NEXT: [[X0:%.*]] = load double, ptr [[LHS_0]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds { double, double }, ptr [[RHS]], i64 [[IV]], i32 0
+; CHECK-NEXT: [[Y0:%.*]] = load double, ptr [[TMP1]], align 8
+; CHECK-NEXT: [[P0:%.*]] = call double @llvm.pow.f64(double [[X0]], double [[Y0]])
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 0
+; CHECK-NEXT: store double [[P0]], ptr [[TMP3]], align 8
+; CHECK-NEXT: [[LHS_1:%.*]] = getelementptr inbounds { double, double }, ptr [[LHS]], i64 [[IV]], i32 1
+; CHECK-NEXT: [[X1:%.*]] = load double, ptr [[LHS_1]], align 8
+; CHECK-NEXT: [[RHS_1:%.*]] = getelementptr inbounds { double, double }, ptr [[RHS]], i64 [[IV]], i32 1
+; CHECK-NEXT: [[Y1:%.*]] = load double, ptr [[RHS_1]], align 8
+; CHECK-NEXT: [[P1:%.*]] = call double @llvm.pow.f64(double [[X1]], double [[Y1]])
+; CHECK-NEXT: [[DST_1:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 1
+; CHECK-NEXT: store double [[P1]], ptr [[DST_1]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[DONE]], label %[[SCALAR_PH]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %lhs.0 = getelementptr inbounds { double, double }, ptr %lhs, i64 %iv, i32 0
+ %x0 = load double, ptr %lhs.0, align 8
+ %rhs.0 = getelementptr inbounds { double, double }, ptr %rhs, i64 %iv, i32 0
+ %y0 = load double, ptr %rhs.0, align 8
+ %p0 = call double @llvm.pow.f64(double %x0, double %y0)
+ %dst.0 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 0
+ store double %p0, ptr %dst.0, align 8
+ %lhs.1 = getelementptr inbounds { double, double }, ptr %lhs, i64 %iv, i32 1
+ %x1 = load double, ptr %lhs.1, align 8
+ %rhs.1 = getelementptr inbounds { double, double }, ptr %rhs, i64 %iv, i32 1
+ %y1 = load double, ptr %rhs.1, align 8
+ %p1 = call double @llvm.pow.f64(double %x1, double %y1)
+ %dst.1 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 1
+ store double %p1, ptr %dst.1, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, %n
+ br i1 %done, label %exit, label %loop
+exit:
+ ret void
+}
+
+
+define void @powi_uniform_operand_defined_in_loop(ptr noalias %src, ptr noalias %dst, i32 %exponent, i64 %n) {
+; CHECK-LABEL: define void @powi_uniform_operand_defined_in_loop(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[EXPONENT:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[UNIFORM_EXPONENT:%.*]] = add i32 [[EXPONENT]], 1
+; CHECK-NEXT: [[SRC_0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 0
+; CHECK-NEXT: [[X0:%.*]] = load double, ptr [[SRC_0]], align 8
+; CHECK-NEXT: [[P0:%.*]] = call double @llvm.powi.f64.i32(double [[X0]], i32 [[UNIFORM_EXPONENT]])
+; CHECK-NEXT: [[DST_0:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 0
+; CHECK-NEXT: store double [[P0]], ptr [[DST_0]], align 8
+; CHECK-NEXT: [[SRC_1:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 1
+; CHECK-NEXT: [[X1:%.*]] = load double, ptr [[SRC_1]], align 8
+; CHECK-NEXT: [[P1:%.*]] = call double @llvm.powi.f64.i32(double [[X1]], i32 [[UNIFORM_EXPONENT]])
+; CHECK-NEXT: [[DST_1:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 1
+; CHECK-NEXT: store double [[P1]], ptr [[DST_1]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %uniform.exponent = add i32 %exponent, 1
+ %src.0 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 0
+ %x0 = load double, ptr %src.0, align 8
+ %p0 = call double @llvm.powi.f64.i32(double %x0, i32 %uniform.exponent)
+ %dst.0 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 0
+ store double %p0, ptr %dst.0, align 8
+ %src.1 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 1
+ %x1 = load double, ptr %src.1, align 8
+ %p1 = call double @llvm.powi.f64.i32(double %x1, i32 %uniform.exponent)
+ %dst.1 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 1
+ store double %p1, ptr %dst.1, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, %n
+ br i1 %done, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @powi_shared_wide_load(ptr noalias %src, ptr noalias %dst, i64 %n) {
+; CHECK-LABEL: define void @powi_shared_wide_load(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH1:.*]]
+; CHECK: [[VECTOR_PH1]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds double, ptr [[SRC]], i64 [[INDEX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP0]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[WIDE_LOAD]], i32 2)
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP5]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1]]
+; CHECK: [[SCALAR_PH1]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SRC_PTR:%.*]] = getelementptr inbounds double, ptr [[SRC]], i64 [[IV]]
+; CHECK-NEXT: [[X:%.*]] = load double, ptr [[SRC_PTR]], align 8
+; CHECK-NEXT: [[P0:%.*]] = call double @llvm.powi.f64.i32(double [[X]], i32 2)
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 0
+; CHECK-NEXT: store double [[P0]], ptr [[TMP2]], align 8
+; CHECK-NEXT: [[P1:%.*]] = call double @llvm.powi.f64.i32(double [[X]], i32 2)
+; CHECK-NEXT: [[DST_1:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 1
+; CHECK-NEXT: store double [[P1]], ptr [[DST_1]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[DONE]], label %[[SCALAR_PH]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %src.ptr = getelementptr inbounds double, ptr %src, i64 %iv
+ %x = load double, ptr %src.ptr, align 8
+ %p0 = call double @llvm.powi.f64.i32(double %x, i32 2)
+ %dst.0 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 0
+ store double %p0, ptr %dst.0, align 8
+ %p1 = call double @llvm.powi.f64.i32(double %x, i32 2)
+ %dst.1 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 1
+ store double %p1, ptr %dst.1, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, %n
+ br i1 %done, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @sincos_struct_return(ptr noalias %src, ptr noalias %dst, i64 %n) {
+; CHECK-LABEL: define void @sincos_struct_return(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH1:.*]]
+; CHECK: [[VECTOR_PH1]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x double>, ptr [[TMP0]], align 8
+; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> [[STRIDED_VEC]])
+; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <2 x double>, <2 x double> } [[TMP1]], 0
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> [[STRIDED_VEC1]])
+; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <2 x double>, <2 x double> } [[TMP4]], 0
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP6]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP8]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1]]
+; CHECK: [[SCALAR_PH1]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_PH]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SRC_0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 0
+; CHECK-NEXT: [[X0:%.*]] = load double, ptr [[SRC_0]], align 8
+; CHECK-NEXT: [[SINCOS0:%.*]] = call { double, double } @llvm.sincos.f64(double [[X0]])
+; CHECK-NEXT: [[SIN0:%.*]] = extractvalue { double, double } [[SINCOS0]], 0
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 0
+; CHECK-NEXT: store double [[SIN0]], ptr [[TMP3]], align 8
+; CHECK-NEXT: [[SRC_1:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 1
+; CHECK-NEXT: [[X1:%.*]] = load double, ptr [[SRC_1]], align 8
+; CHECK-NEXT: [[SINCOS1:%.*]] = call { double, double } @llvm.sincos.f64(double [[X1]])
+; CHECK-NEXT: [[SIN1:%.*]] = extractvalue { double, double } [[SINCOS1]], 0
+; CHECK-NEXT: [[DST_1:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 1
+; CHECK-NEXT: store double [[SIN1]], ptr [[DST_1]], align 8
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[DONE]], label %[[SCALAR_PH]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %src.0 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 0
+ %x0 = load double, ptr %src.0, align 8
+ %sincos0 = call { double, double } @llvm.sincos.f64(double %x0)
+ %sin0 = extractvalue { double, double } %sincos0, 0
+ %dst.0 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 0
+ store double %sin0, ptr %dst.0, align 8
+ %src.1 = getelementptr inbounds { double, double }, ptr %src, i64 %iv, i32 1
+ %x1 = load double, ptr %src.1, align 8
+ %sincos1 = call { double, double } @llvm.sincos.f64(double %x1)
+ %sin1 = extractvalue { double, double } %sincos1, 0
+ %dst.1 = getelementptr inbounds { double, double }, ptr %dst, i64 %iv, i32 1
+ store double %sin1, ptr %dst.1, align 8
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, %n
+ br i1 %done, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
+; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
+; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
+; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
+; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
+; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
+; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
+; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]}
+;.
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory-intrinsics.ll
new file mode 100644
index 0000000000000..bb4873bc0aefe
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory-intrinsics.ll
@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -passes=loop-vectorize -mattr=+v -S %s | FileCheck %s
+
+target triple="riscv64-gnu-linux"
+define void @strided_load_feeding_interleave_store(ptr noalias %src, ptr noalias %dst) {
+; CHECK-LABEL: define void @strided_load_feeding_interleave_store(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
+; CHECK-NEXT: [[TMP6:%.*]] = shl nuw i64 [[INDEX]], 5
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr nuw i8, ptr [[SRC]], i64 [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP7]], i64 32, <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i32], ptr [[DST]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP9]], i64 0, i64 0
+; CHECK-NEXT: [[INTERLEAVE_EVL:%.*]] = mul nuw nsw i32 [[TMP5]], 4
+; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call <vscale x 16 x i32> @llvm.vector.interleave4.nxv16i32(<vscale x 4 x i32> [[TMP8]], <vscale x 4 x i32> [[TMP8]], <vscale x 4 x i32> [[TMP8]], <vscale x 4 x i32> [[TMP8]])
+; CHECK-NEXT: call void @llvm.vp.store.nxv16i32.p0(<vscale x 16 x i32> [[INTERLEAVED_VEC]], ptr align 4 [[TMP10]], <vscale x 16 x i1> splat (i1 true), i32 [[INTERLEAVE_EVL]])
+; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP5]] to i64
+; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP11]], [[INDEX]]
+; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]]
+; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
+; CHECK-NEXT: br i1 [[TMP12]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %src.idx = shl nuw nsw i64 %iv, 3
+ %src.ptr = getelementptr inbounds i32, ptr %src, i64 %src.idx
+ %value = load i32, ptr %src.ptr, align 4
+ %dst.ptr = getelementptr inbounds [4 x i32], ptr %dst, i64 %iv
+ %dst.0 = getelementptr inbounds [4 x i32], ptr %dst.ptr, i64 0, i64 0
+ store i32 %value, ptr %dst.0, align 4
+ %dst.1 = getelementptr inbounds [4 x i32], ptr %dst.ptr, i64 0, i64 1
+ store i32 %value, ptr %dst.1, align 4
+ %dst.2 = getelementptr inbounds [4 x i32], ptr %dst.ptr, i64 0, i64 2
+ store i32 %value, ptr %dst.2, align 4
+ %dst.3 = getelementptr inbounds [4 x i32], ptr %dst.ptr, i64 0, i64 3
+ store i32 %value, ptr %dst.3, align 4
+ %iv.next = add nuw nsw i64 %iv, 1
+ %done = icmp eq i64 %iv.next, 1024
+ br i1 %done, label %exit, label %loop
+
+exit:
+ ret void
+}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+;.
>From d7bdc0e9ef017f65c6c98876e2ece41d078d540c Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Mon, 13 Jul 2026 12:21:04 +0000
Subject: [PATCH 2/2] [LV] Extend narrowinterleave group for intrinsics
---
.../Transforms/Vectorize/VPlanTransforms.cpp | 44 +++++-
...w-interleave-to-widen-memory-intrinsics.ll | 140 +++++++++---------
2 files changed, 104 insertions(+), 80 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index f8198cf9133bf..eb347e848b806 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -5874,15 +5874,24 @@ static bool canNarrowLoad(VPSingleDefRecipe *WideMember0, unsigned OpIdx,
return false;
}
-static bool canNarrowOps(ArrayRef<VPValue *> Ops, bool IsScalable) {
+static bool canNarrowOps(ArrayRef<VPValue *> Ops, bool IsScalable,
+ const TargetTransformInfo &TTI) {
SmallVector<VPValue *> Ops0;
auto *WideMember0 = dyn_cast<VPRecipeWithIRFlags>(Ops[0]);
if (!WideMember0)
return false;
for (VPValue *V : Ops) {
- if (!isa<VPWidenRecipe, VPWidenCastRecipe>(V))
+ if (!isa<VPWidenRecipe, VPWidenCastRecipe, VPWidenIntrinsicRecipe>(V))
return false;
auto *R = cast<VPRecipeWithIRFlags>(V);
+ if (auto *IntrinsicR = dyn_cast<VPWidenIntrinsicRecipe>(R)) {
+ if (IntrinsicR->mayReadFromMemory() || IntrinsicR->mayHaveSideEffects() ||
+ R->getScalarType()->isAggregateType() ||
+ any_of(R->operands(), [](VPValue *Op) {
+ return Op->getScalarType()->isAggregateType();
+ }))
+ return false;
+ }
if (getOpcodeOrIntrinsicID(R) != getOpcodeOrIntrinsicID(WideMember0))
return false;
if (R->getScalarType() != WideMember0->getScalarType())
@@ -5896,7 +5905,16 @@ static bool canNarrowOps(ArrayRef<VPValue *> Ops, bool IsScalable) {
for (VPValue *Op : Ops)
OpsI.push_back(Op->getDefiningRecipe()->getOperand(Idx));
- if (canNarrowOps(OpsI, IsScalable))
+ auto *WideIntrinsic0 = dyn_cast<VPWidenIntrinsicRecipe>(WideMember0);
+ if (WideIntrinsic0 &&
+ isVectorIntrinsicWithScalarOpAtArg(
+ WideIntrinsic0->getVectorIntrinsicID(), Idx, &TTI)) {
+ if (!all_of(OpsI, equal_to(OpsI.front())))
+ return false;
+ continue;
+ }
+
+ if (canNarrowOps(OpsI, IsScalable, TTI))
continue;
if (any_of(enumerate(OpsI), [WideMember0, Idx, IsScalable](const auto &P) {
@@ -5970,7 +5988,8 @@ static bool isAlreadyNarrow(VPValue *VPV) {
// Preheader.
static VPValue *narrowInterleaveGroupOp(ArrayRef<VPValue *> Members,
SmallPtrSetImpl<VPValue *> &NarrowedOps,
- VPBasicBlock *Preheader) {
+ VPBasicBlock *Preheader,
+ const TargetTransformInfo &TTI) {
VPValue *V = Members.front();
if (NarrowedOps.contains(V))
return V;
@@ -5992,7 +6011,7 @@ static VPValue *narrowInterleaveGroupOp(ArrayRef<VPValue *> Members,
return V;
VPRecipeBase *R = V->getDefiningRecipe();
- if (isa<VPWidenRecipe, VPWidenCastRecipe>(R)) {
+ if (isa<VPWidenRecipe, VPWidenCastRecipe, VPWidenIntrinsicRecipe>(R)) {
auto *WideMember0 = cast<VPRecipeWithIRFlags>(R);
for (VPValue *Member : Members.drop_front())
WideMember0->intersectFlags(*cast<VPRecipeWithIRFlags>(Member));
@@ -6000,8 +6019,17 @@ static VPValue *narrowInterleaveGroupOp(ArrayRef<VPValue *> Members,
SmallVector<VPValue *> OpsI;
for (VPValue *Member : Members)
OpsI.push_back(Member->getDefiningRecipe()->getOperand(Idx));
+ auto *WideIntrinsic0 = dyn_cast<VPWidenIntrinsicRecipe>(WideMember0);
+ if (WideIntrinsic0 &&
+ isVectorIntrinsicWithScalarOpAtArg(
+ WideIntrinsic0->getVectorIntrinsicID(), Idx, &TTI)) {
+ assert(all_of(OpsI, equal_to(OpsI.front())) &&
+ "scalar intrinsic operands must match");
+ WideMember0->setOperand(Idx, OpsI.front());
+ continue;
+ }
WideMember0->setOperand(
- Idx, narrowInterleaveGroupOp(OpsI, NarrowedOps, Preheader));
+ Idx, narrowInterleaveGroupOp(OpsI, NarrowedOps, Preheader, TTI));
}
return V;
}
@@ -6137,7 +6165,7 @@ VPlanTransforms::narrowInterleaveGroups(VPlan &Plan,
// Check if all values feeding InterleaveR are matching wide recipes, which
// operands that can be narrowed.
if (!canNarrowOps(InterleaveR->getStoredValues(),
- VFToOptimize->isScalable()))
+ VFToOptimize->isScalable(), TTI))
return nullptr;
StoreGroups.push_back(InterleaveR);
}
@@ -6170,7 +6198,7 @@ VPlanTransforms::narrowInterleaveGroups(VPlan &Plan,
// Narrow operation tree rooted at store groups.
for (auto *StoreGroup : StoreGroups) {
VPValue *Res = narrowInterleaveGroupOp(StoreGroup->getStoredValues(),
- NarrowedOps, Preheader);
+ NarrowedOps, Preheader, TTI);
auto *SI =
cast<StoreInst>(StoreGroup->getInterleaveGroup()->getInsertPos());
auto *S = new VPWidenStoreRecipe(*SI, StoreGroup->getAddr(), Res, nullptr,
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll
index 626a8212adfe0..e006448266f4e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-intrinsics.ll
@@ -6,36 +6,27 @@ target triple = "arm64-apple-macosx"
define void @powi_two_fields_same_exponent(ptr noalias %src, ptr noalias %dst, i64 %n) {
; CHECK-LABEL: define void @powi_two_fields_same_exponent(
; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
-; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: [[VECTOR_PH:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH1:.*]]
; CHECK: [[VECTOR_PH1]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[INDEX]], i32 0
-; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x double>, ptr [[TMP0]], align 8
-; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 0, i32 2>
-; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT: [[STRIDED_VEC:%.*]] = load <2 x double>, ptr [[TMP0]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[STRIDED_VEC]], i32 2)
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[STRIDED_VEC1]], i32 2)
-; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP4]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP6]], align 8
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[TMP6]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1]]
+; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
; CHECK: [[SCALAR_PH1]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_PH]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[SRC_0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 0
; CHECK-NEXT: [[X0:%.*]] = load double, ptr [[SRC_0]], align 8
; CHECK-NEXT: [[P0:%.*]] = call double @llvm.powi.f64.i32(double [[X0]], i32 2)
@@ -150,40 +141,29 @@ exit:
define void @pow_two_fields_two_vector_operands(ptr noalias %lhs, ptr noalias %rhs, ptr noalias %dst, i64 %n) {
; CHECK-LABEL: define void @pow_two_fields_two_vector_operands(
; CHECK-SAME: ptr noalias [[LHS:%.*]], ptr noalias [[RHS:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
-; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: [[VECTOR_PH:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH1:.*]]
; CHECK: [[VECTOR_PH1]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds { double, double }, ptr [[LHS]], i64 [[INDEX]], i32 0
-; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x double>, ptr [[TMP0]], align 8
-; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 0, i32 2>
-; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x double> [[WIDE_VEC]], <4 x double> poison, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT: [[STRIDED_VEC:%.*]] = load <2 x double>, ptr [[TMP0]], align 8
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { double, double }, ptr [[RHS]], i64 [[INDEX]], i32 0
-; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <4 x double>, ptr [[TMP7]], align 8
-; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x double> [[WIDE_VEC2]], <4 x double> poison, <2 x i32> <i32 0, i32 2>
-; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x double> [[WIDE_VEC2]], <4 x double> poison, <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = load <2 x double>, ptr [[TMP7]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> [[STRIDED_VEC]], <2 x double> [[STRIDED_VEC3]])
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> [[STRIDED_VEC1]], <2 x double> [[STRIDED_VEC4]])
-; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP8]], align 8
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[TMP8]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1]]
+; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
; CHECK: [[SCALAR_PH1]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_PH]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[LHS_0:%.*]] = getelementptr inbounds { double, double }, ptr [[LHS]], i64 [[IV]], i32 0
; CHECK-NEXT: [[X0:%.*]] = load double, ptr [[LHS_0]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds { double, double }, ptr [[RHS]], i64 [[IV]], i32 0
@@ -234,10 +214,28 @@ exit:
define void @powi_uniform_operand_defined_in_loop(ptr noalias %src, ptr noalias %dst, i32 %exponent, i64 %n) {
; CHECK-LABEL: define void @powi_uniform_operand_defined_in_loop(
; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[EXPONENT:%.*]], i64 [[N:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[EXPONENT]], 1
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP1]], align 8
+; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[WIDE_LOAD]], i32 [[TMP0]])
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
+; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[TMP3]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[UNIFORM_EXPONENT:%.*]] = add i32 [[EXPONENT]], 1
; CHECK-NEXT: [[SRC_0:%.*]] = getelementptr inbounds { double, double }, ptr [[SRC]], i64 [[IV]], i32 0
; CHECK-NEXT: [[X0:%.*]] = load double, ptr [[SRC_0]], align 8
@@ -251,7 +249,7 @@ define void @powi_uniform_operand_defined_in_loop(ptr noalias %src, ptr noalias
; CHECK-NEXT: store double [[P1]], ptr [[DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
@@ -282,45 +280,41 @@ exit:
define void @powi_shared_wide_load(ptr noalias %src, ptr noalias %dst, i64 %n) {
; CHECK-LABEL: define void @powi_shared_wide_load(
; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
-; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: [[VECTOR_PH:.*:]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH1:.*]], label %[[VECTOR_PH1:.*]]
-; CHECK: [[VECTOR_PH1]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
-; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
-; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds double, ptr [[SRC]], i64 [[INDEX]]
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP0]], align 8
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[WIDE_LOAD]], i32 2)
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[INDEX]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
-; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP5]], align 8
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1:.*]]
; CHECK: [[SCALAR_PH1]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_PH]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH1]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[SRC_PTR:%.*]] = getelementptr inbounds double, ptr [[SRC]], i64 [[IV]]
-; CHECK-NEXT: [[X:%.*]] = load double, ptr [[SRC_PTR]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[SRC_PTR]], align 8
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x double> [[BROADCAST_SPLATINSERT]], <2 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> [[BROADCAST_SPLAT]], i32 2)
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 0
+; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[TMP3]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 1
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N]]
+; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: br label %[[EXIT:.*]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br label %[[LOOP1:.*]]
+; CHECK: [[LOOP1]]:
+; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP1]] ]
+; CHECK-NEXT: [[SRC_PTR1:%.*]] = getelementptr inbounds double, ptr [[SRC]], i64 [[IV1]]
+; CHECK-NEXT: [[X:%.*]] = load double, ptr [[SRC_PTR1]], align 8
; CHECK-NEXT: [[P0:%.*]] = call double @llvm.powi.f64.i32(double [[X]], i32 2)
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 0
-; CHECK-NEXT: store double [[P0]], ptr [[TMP2]], align 8
+; CHECK-NEXT: [[DST_0:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV1]], i32 0
+; CHECK-NEXT: store double [[P0]], ptr [[DST_0]], align 8
; CHECK-NEXT: [[P1:%.*]] = call double @llvm.powi.f64.i32(double [[X]], i32 2)
-; CHECK-NEXT: [[DST_1:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV]], i32 1
+; CHECK-NEXT: [[DST_1:%.*]] = getelementptr inbounds { double, double }, ptr [[DST]], i64 [[IV1]], i32 1
; CHECK-NEXT: store double [[P1]], ptr [[DST_1]], align 8
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1
; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[DONE]], label %[[SCALAR_PH]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
-; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
entry:
@@ -370,7 +364,7 @@ define void @sincos_struct_return(ptr noalias %src, ptr noalias %dst, i64 %n) {
; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP8]], align 8
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[SCALAR_PH:.*]], label %[[SCALAR_PH1]]
@@ -393,7 +387,7 @@ define void @sincos_struct_return(ptr noalias %src, ptr noalias %dst, i64 %n) {
; CHECK-NEXT: store double [[SIN1]], ptr [[DST_1]], align 8
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[DONE]], label %[[SCALAR_PH]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-NEXT: br i1 [[DONE]], label %[[SCALAR_PH]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: ret void
;
@@ -435,4 +429,6 @@ exit:
; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]}
+; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]}
+; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META2]], [[META1]]}
;.
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