[llvm] [AMDGPU] Refactor GFX11 VALU Mask Hazard Waitcnt Merging (PR #169213)

[Jay Foad via llvm-commits]

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@@ -464,6 +577,11 @@ class AMDGPUWaitSGPRHazards {
     MRI = &MF.getRegInfo();
     DsNopCount = ST->isWave64() ? WAVE64_NOPS : WAVE32_NOPS;
 
+    // VALU mask write hazards have already been handled, but this pass
+    // performs a forward scan to optimize them.
+    if (ST->hasVALUMaskWriteHazard())
+      return ST->isWave64() ? runWaitMerging(MF) : false;
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jayfoad wrote:

I don't really get why it's OK to return here and skip the stuff below. Are there any targets that have both hasVALUReadSGPRHazard and hasVALUMaskWriteHazard or are they mutually exclusive?

https://github.com/llvm/llvm-project/pull/169213