[llvm] [NFC][LLVM][CodeGen][SVE] Strengthen the isel definition of AArch64setcc_z. (PR #209170)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 05:52:49 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Paul Walker (paulwalker-arm)
<details>
<summary>Changes</summary>
Making all operand types derive from the compare's LHS reduces the number of types an isel rule must specify, which improves readability.
---
Full diff: https://github.com/llvm/llvm-project/pull/209170.diff
2 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (+8-8)
- (modified) llvm/lib/Target/AArch64/SVEInstrFormats.td (+74-98)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 4712406e37e6b..8d6ab0540e9f2 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -777,14 +777,14 @@ let Predicates = [HasSVE_or_SME] in {
defm FNEG_ZPmZ : sve_int_un_pred_arit_bitwise_fp<0b101, "fneg", AArch64fneg_mt>;
// zext(cmpeq(x, splat(0))) -> cnot(x)
- def : Pat<(nxv16i8 (zext (nxv16i1 (AArch64setcc_z (nxv16i1 (SVEAllActive):$Pg), nxv16i8:$Op2, (SVEDup0), SETEQ)))),
- (CNOT_ZPmZ_B $Op2, $Pg, $Op2)>;
- def : Pat<(nxv8i16 (zext (nxv8i1 (AArch64setcc_z (nxv8i1 (SVEAllActive):$Pg), nxv8i16:$Op2, (SVEDup0), SETEQ)))),
- (CNOT_ZPmZ_H $Op2, $Pg, $Op2)>;
- def : Pat<(nxv4i32 (zext (nxv4i1 (AArch64setcc_z (nxv4i1 (SVEAllActive):$Pg), nxv4i32:$Op2, (SVEDup0), SETEQ)))),
- (CNOT_ZPmZ_S $Op2, $Pg, $Op2)>;
- def : Pat<(nxv2i64 (zext (nxv2i1 (AArch64setcc_z (nxv2i1 (SVEAllActive):$Pg), nxv2i64:$Op2, (SVEDup0), SETEQ)))),
- (CNOT_ZPmZ_D $Op2, $Pg, $Op2)>;
+ def : Pat<(nxv16i8 (zext (AArch64setcc_z (SVEAllActive):$Pg, nxv16i8:$LHS, (SVEDup0), SETEQ))),
+ (CNOT_ZPmZ_B $LHS, $Pg, $LHS)>;
+ def : Pat<(nxv8i16 (zext (AArch64setcc_z (SVEAllActive):$Pg, nxv8i16:$LHS, (SVEDup0), SETEQ))),
+ (CNOT_ZPmZ_H $LHS, $Pg, $LHS)>;
+ def : Pat<(nxv4i32 (zext (AArch64setcc_z (SVEAllActive):$Pg, nxv4i32:$LHS, (SVEDup0), SETEQ))),
+ (CNOT_ZPmZ_S $LHS, $Pg, $LHS)>;
+ def : Pat<(nxv2i64 (zext (AArch64setcc_z (SVEAllActive):$Pg, nxv2i64:$LHS, (SVEDup0), SETEQ))),
+ (CNOT_ZPmZ_D $LHS, $Pg, $LHS)>;
defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax", "SMAX_ZPZZ", AArch64smax_m1, DestructiveBinaryComm>;
defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax", "UMAX_ZPZZ", AArch64umax_m1, DestructiveBinaryComm>;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index f96702a01c277..6c469097cc9c1 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -113,8 +113,10 @@ class SVEType<ValueType VT> {
}
def SDT_AArch64Setcc : SDTypeProfile<1, 4, [
- SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>,
- SDTCVecEltisVT<0, i1>, SDTCVecEltisVT<1, i1>, SDTCisSameAs<2, 3>,
+ SDTCisVec<0>, SDTCisSameNumEltsAs<0, 2>, SDTCVecEltisVT<0, i1>,
+ SDTCisSameAs<1, 0>,
+ SDTCisVec<2>,
+ SDTCisSameAs<3, 2>,
SDTCisVT<4, OtherVT>
]>;
@@ -5789,28 +5791,28 @@ class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm,
let DestructiveInstType = DestructivePredicate;
}
-multiclass SVE_SETCC_Pat<CondCode cc, CondCode invcc, ValueType predvt,
- ValueType intvt, Instruction cmp> {
- def : Pat<(predvt (AArch64setcc_z predvt:$Op1, intvt:$Op2, intvt:$Op3, cc)),
- (cmp $Op1, $Op2, $Op3)>;
- def : Pat<(predvt (AArch64setcc_z predvt:$Op1, intvt:$Op2, intvt:$Op3, invcc)),
- (cmp $Op1, $Op3, $Op2)>;
- def : Pat<(predvt (and predvt:$Pg, (AArch64setcc_z_oneuse (predvt (SVEAllActive)), intvt:$Op2, intvt:$Op3, cc))),
- (cmp $Pg, $Op2, $Op3)>;
- def : Pat<(predvt (and predvt:$Pg, (AArch64setcc_z_oneuse (predvt (SVEAllActive)), intvt:$Op2, intvt:$Op3, invcc))),
- (cmp $Pg, $Op3, $Op2)>;
+multiclass SVE_SETCC_Pat<CondCode cc, CondCode invcc, ValueType vt,
+ Instruction cmp> {
+ def : Pat<(AArch64setcc_z PPR:$Pg, vt:$LHS, vt:$RHS, cc),
+ (cmp $Pg, $LHS, $RHS)>;
+ def : Pat<(AArch64setcc_z PPR:$Pg, vt:$LHS, vt:$RHS, invcc),
+ (cmp $Pg, $RHS, $LHS)>;
+ def : Pat<(and PPR:$Pg, (AArch64setcc_z_oneuse (SVEAllActive), vt:$LHS, vt:$RHS, cc)),
+ (cmp $Pg, $LHS, $RHS)>;
+ def : Pat<(and PPR:$Pg, (AArch64setcc_z_oneuse (SVEAllActive), vt:$LHS, vt:$RHS, invcc)),
+ (cmp $Pg, $RHS, $LHS)>;
}
-multiclass SVE_SETCC_Pat_With_Zero<CondCode cc, CondCode invcc, ValueType predvt,
- ValueType intvt, Instruction cmp> {
- def : Pat<(predvt (AArch64setcc_z predvt:$Op1, intvt:$Op2, (SVEDup0), cc)),
- (cmp $Op1, $Op2)>;
- def : Pat<(predvt (AArch64setcc_z predvt:$Op1, (SVEDup0), intvt:$Op2, invcc)),
- (cmp $Op1, $Op2)>;
- def : Pat<(predvt (and predvt:$Pg, (AArch64setcc_z_oneuse (predvt (SVEAllActive)), intvt:$Op1, (SVEDup0), cc))),
- (cmp $Pg, $Op1)>;
- def : Pat<(predvt (and predvt:$Pg, (AArch64setcc_z_oneuse (predvt (SVEAllActive)), (SVEDup0), intvt:$Op1, invcc))),
- (cmp $Pg, $Op1)>;
+multiclass SVE_SETCC_Pat_With_Zero<CondCode cc, CondCode invcc, ValueType vt,
+ Instruction cmp> {
+ def : Pat<(AArch64setcc_z PPR:$Pg, vt:$LHS, (SVEDup0), cc),
+ (cmp $Pg, $LHS)>;
+ def : Pat<(AArch64setcc_z PPR:$Pg, (SVEDup0), vt:$RHS, invcc),
+ (cmp $Pg, $RHS)>;
+ def : Pat<(and PPR:$Pg, (AArch64setcc_z_oneuse (SVEAllActive), vt:$LHS, (SVEDup0), cc)),
+ (cmp $Pg, $LHS)>;
+ def : Pat<(and PPR:$Pg, (AArch64setcc_z_oneuse (SVEAllActive), (SVEDup0), vt:$RHS, invcc)),
+ (cmp $Pg, $RHS)>;
}
multiclass sve_int_cmp_0<bits<3> opc, string asm, CondCode cc, CondCode invcc> {
@@ -5819,10 +5821,10 @@ multiclass sve_int_cmp_0<bits<3> opc, string asm, CondCode cc, CondCode invcc> {
def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>;
def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>;
- defm : SVE_SETCC_Pat<cc, invcc, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
- defm : SVE_SETCC_Pat<cc, invcc, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat<cc, invcc, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Pat<cc, invcc, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
+ defm : SVE_SETCC_Pat<cc, invcc, nxv16i8, !cast<Instruction>(NAME # _B)>;
+ defm : SVE_SETCC_Pat<cc, invcc, nxv8i16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat<cc, invcc, nxv4i32, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Pat<cc, invcc, nxv2i64, !cast<Instruction>(NAME # _D)>;
}
multiclass sve_int_cmp_0_wide<bits<3> opc, string asm, SDPatternOperator op> {
@@ -5845,7 +5847,6 @@ multiclass sve_int_cmp_1_wide<bits<3> opc, string asm, SDPatternOperator op> {
def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>;
}
-
//===----------------------------------------------------------------------===//
// SVE Integer Compare - Signed Immediate Group
//===----------------------------------------------------------------------===//
@@ -5880,50 +5881,30 @@ class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
let DestructiveInstType = DestructivePredicate;
}
-multiclass SVE_SETCC_Imm_Pat<CondCode cc, CondCode commuted_cc,
- ValueType predvt, ValueType intvt,
+multiclass SVE_SETCC_Imm_Pat<CondCode cc, CondCode invcc, ValueType vt,
Operand immtype, Instruction cmp> {
- def : Pat<(predvt (AArch64setcc_z (predvt PPR_3b:$Pg),
- (intvt ZPR:$Zs1),
- (intvt (splat_vector (immtype:$imm))),
- cc)),
- (cmp $Pg, $Zs1, immtype:$imm)>;
- def : Pat<(predvt (AArch64setcc_z (predvt PPR_3b:$Pg),
- (intvt (splat_vector (immtype:$imm))),
- (intvt ZPR:$Zs1),
- commuted_cc)),
- (cmp $Pg, $Zs1, immtype:$imm)>;
- def : Pat<(predvt (and predvt:$Pg,
- (AArch64setcc_z_oneuse (predvt (SVEAllActive)),
- (intvt ZPR:$Zs1),
- (intvt (splat_vector (immtype:$imm))),
- cc))),
- (cmp $Pg, $Zs1, immtype:$imm)>;
- def : Pat<(predvt (and predvt:$Pg,
- (AArch64setcc_z_oneuse (predvt (SVEAllActive)),
- (intvt (splat_vector (immtype:$imm))),
- (intvt ZPR:$Zs1),
- commuted_cc))),
- (cmp $Pg, $Zs1, immtype:$imm)>;
-}
-
-multiclass sve_int_scmp_vi<bits<3> opc, string asm, CondCode cc, CondCode commuted_cc> {
+ def : Pat<(AArch64setcc_z PPR:$Pg, vt:$LHS, (splat_vector (immtype:$imm)), cc),
+ (cmp $Pg, $LHS, immtype:$imm)>;
+ def : Pat<(AArch64setcc_z PPR:$Pg, (splat_vector (immtype:$imm)), vt:$RHS, invcc),
+ (cmp $Pg, $RHS, immtype:$imm)>;
+ def : Pat<(and PPR:$Pg, (AArch64setcc_z_oneuse (SVEAllActive), vt:$LHS, (splat_vector (immtype:$imm)), cc)),
+ (cmp $Pg, $LHS, immtype:$imm)>;
+ def : Pat<(and PPR:$Pg, (AArch64setcc_z_oneuse (SVEAllActive), (splat_vector (immtype:$imm)), vt:$RHS, invcc)),
+ (cmp $Pg, $RHS, immtype:$imm)>;
+}
+
+multiclass sve_int_scmp_vi<bits<3> opc, string asm, CondCode cc, CondCode invcc> {
def _B : sve_int_scmp_vi<0b00, opc, asm, PPR8, ZPR8, simm5_32b>;
def _H : sve_int_scmp_vi<0b01, opc, asm, PPR16, ZPR16, simm5_32b>;
def _S : sve_int_scmp_vi<0b10, opc, asm, PPR32, ZPR32, simm5_32b>;
def _D : sve_int_scmp_vi<0b11, opc, asm, PPR64, ZPR64, simm5_64b>;
- defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv16i1, nxv16i8, simm5_32b,
- !cast<Instruction>(NAME # _B)>;
- defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv8i1, nxv8i16, simm5_32b,
- !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv4i1, nxv4i32, simm5_32b,
- !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv2i1, nxv2i64, simm5_64b,
- !cast<Instruction>(NAME # _D)>;
+ defm : SVE_SETCC_Imm_Pat<cc, invcc, nxv16i8, simm5_32b, !cast<Instruction>(NAME # _B)>;
+ defm : SVE_SETCC_Imm_Pat<cc, invcc, nxv8i16, simm5_32b, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Imm_Pat<cc, invcc, nxv4i32, simm5_32b, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Imm_Pat<cc, invcc, nxv2i64, simm5_64b, !cast<Instruction>(NAME # _D)>;
}
-
//===----------------------------------------------------------------------===//
// SVE Integer Compare - Unsigned Immediate Group
//===----------------------------------------------------------------------===//
@@ -5956,23 +5937,18 @@ class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty,
}
multiclass sve_int_ucmp_vi<bits<2> opc, string asm, CondCode cc,
- CondCode commuted_cc> {
+ CondCode invcc> {
def _B : sve_int_ucmp_vi<0b00, opc, asm, PPR8, ZPR8, imm0_127>;
def _H : sve_int_ucmp_vi<0b01, opc, asm, PPR16, ZPR16, imm0_127>;
def _S : sve_int_ucmp_vi<0b10, opc, asm, PPR32, ZPR32, imm0_127>;
def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127_64b>;
- defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv16i1, nxv16i8, imm0_127,
- !cast<Instruction>(NAME # _B)>;
- defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv8i1, nxv8i16, imm0_127,
- !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv4i1, nxv4i32, imm0_127,
- !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv2i1, nxv2i64, imm0_127_64b,
- !cast<Instruction>(NAME # _D)>;
+ defm : SVE_SETCC_Imm_Pat<cc, invcc, nxv16i8, imm0_127, !cast<Instruction>(NAME # _B)>;
+ defm : SVE_SETCC_Imm_Pat<cc, invcc, nxv8i16, imm0_127, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Imm_Pat<cc, invcc, nxv4i32, imm0_127, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Imm_Pat<cc, invcc, nxv2i64, imm0_127_64b, !cast<Instruction>(NAME # _D)>;
}
-
//===----------------------------------------------------------------------===//
// SVE Integer Compare - Scalars Group
//===----------------------------------------------------------------------===//
@@ -6231,19 +6207,19 @@ multiclass sve_fp_3op_p_pd_cc<bits<3> opc, string asm,
def _S : sve_fp_3op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
def _D : sve_fp_3op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
- defm : SVE_SETCC_Pat<cc1, invcc1, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat<cc1, invcc1, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat<cc1, invcc1, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat<cc1, invcc1, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Pat<cc1, invcc1, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Pat<cc1, invcc1, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
+ defm : SVE_SETCC_Pat<cc1, invcc1, nxv8f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat<cc1, invcc1, nxv4f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat<cc1, invcc1, nxv2f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat<cc1, invcc1, nxv4f32, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Pat<cc1, invcc1, nxv2f32, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Pat<cc1, invcc1, nxv2f64, !cast<Instruction>(NAME # _D)>;
- defm : SVE_SETCC_Pat<cc2, invcc2, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat<cc2, invcc2, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat<cc2, invcc2, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat<cc2, invcc2, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Pat<cc2, invcc2, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Pat<cc2, invcc2, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
+ defm : SVE_SETCC_Pat<cc2, invcc2, nxv8f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat<cc2, invcc2, nxv4f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat<cc2, invcc2, nxv2f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat<cc2, invcc2, nxv4f32, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Pat<cc2, invcc2, nxv2f32, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Pat<cc2, invcc2, nxv2f64, !cast<Instruction>(NAME # _D)>;
}
//===----------------------------------------------------------------------===//
@@ -6280,19 +6256,19 @@ multiclass sve_fp_2op_p_pd<bits<3> opc, string asm,
def _S : sve_fp_2op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
def _D : sve_fp_2op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
- defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
-
- defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>;
- defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
- defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv8f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv4f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv2f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv4f32, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv2f32, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc1, invcc1, nxv2f64, !cast<Instruction>(NAME # _D)>;
+
+ defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv8f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv4f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv2f16, !cast<Instruction>(NAME # _H)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv4f32, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv2f32, !cast<Instruction>(NAME # _S)>;
+ defm : SVE_SETCC_Pat_With_Zero<cc2, invcc2, nxv2f64, !cast<Instruction>(NAME # _D)>;
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/209170
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